> Version 8 firmware
> 
> Analysing R37_* data files (see https://elog.ph.ed.ac.uk/AIDA/160)
> 
> Usinmg MIDASsort, I generate a spectrum showing the time difference (10ns clock cycles)
> between sequential ADC data items. There is an offset of 1000.
> 
> I observe peaks at 1000, 1200, 1400 etc - as expected
> 
> I also observe peaks at +/-10 clock cycles relative to these main peaks - not expected
> 
> I also observe some discrete intermediate peaks - not expected 

I have investigated this timing using a sort program and R37_0.

If I only work with data from one module there is no problem. Peaks in the time difference spectrum are the
expected 200 apart.

If I then include a second module's ADC data the time difference spectrum starts to look as the one  Tom attached
but with a fixed 45 ticks offset from the '200' peaks.

I conclude the spectra appearance is due to the 500KHz ASIC readout clocks not being synchronized between the
different FEE64 modules.