AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
AIDA
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Entry time:
Mon Mar 14 11:27:47 2016
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<p>During 'SETUP' the ASIC readout clock ( 500KHz ) is synchronised to the SYNC pulse in V8.10 and later versions of the VHDL.</p> <p>Attached is a short run for verification.</p> <p> </p>
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