AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
AIDA
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Entry time:
Fri Oct 24 15:05:28 2014
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<p> New VHDL loaded in NNAIDA#11,#12,#13,#14: /MIDAS/Aida/FEE_Riken_Apr14_21.bin</p> <div> </div> <div>The code introduces the feature of turning ON or OFF individual ASICs in a FEE64 card. This is achieved by turning off the clock signal to a individual ASIC, which then will not produce any data.</div> <div> </div> <div>Feature controled through "ASIC readout bugger and control", by register onn base address 0x300 and offset 7 (until now 'ASIC readout enable'). </div> <div> </div> <div>Only basic tests of new VHDL were done, but the system seems to be working as before and the operation of turning off individual ASICs works as expected. Screenshot is sample of turning off ASIC3 in NNAIDA#12.</div> <div> </div> <div><a href="141024_150524/turn_off_nnaida12_asic3.png?lb=AIDA"><img border="0" alt="turn_off_nnaida12_asic3.png" src="141024_150524/turn_off_nnaida12_asic3.png?lb=AIDA&thumb=1" name="att0" id="att0" /></a></div>
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