AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
AIDA
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Entry time:
Wed Apr 2 01:41:43 2025
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<p>18/02/15</p> <p>1300: Error seen when trying to check ASIC settings. See Attachment #1. Power cycle removed error.</p> <p> nnaida3 still performing much better than other three cards connected to detector (nnaida1,6,8). Why?</p> <p> Noticed nnaida3 was connected to only adapter PCB which did not feature a metal shielding plate on the front?</p> <p> Noise in other cards caused by possible short or capacitance between PCB pins and shielding plate?</p> <p> -> Removed all shielding plates and no difference seen. Pulser peak widths all still approximately the same.</p> <p> nnaida3+6 PCB grounds connected by thin braid, as well as nnaida1+8. These were all removed. No change.</p> <p> </p> <p>1830: Still seeing errors when data is sent through them Merger, see attachments #2-6.</p> <p> Attached heavy duty copper braiding in loop, connecting all nnaida PCBs in use. Improved FWHM of nnaida1 by factor of 2. No change in other nnaida.</p> <p> Moved kapton and bias from nnaida3 to nnaida11 (same crate, next module along) and saw no appreciable difference in the spectra.</p> <p> Changed voltages in PSUs for first 16 nnaida.</p> <p> +5V -> +5.5V, -6V -> -6.5V, +7V -> +8V.</p> <p> All +5.5V rails at 5.5V, however in PSU#1 (supplying inner FEE modules) -6.5V and +8V rails show variations of +- ~12mV and +- ~4mV respectively, between outlets.</p> <p> Installed PSUs with updated voltages.</p> <p> nnaida8 FWHM improved by factor of 2 but no difference in other nnaida.</p> <p> Current configuration nnaida1,6,8,11. nnaida1+8 connected to p+n side, nnaida6+11 connected to n+n side.</p> <p> Current FWHM: nnaida1 ~500ch, nnaida6 ~1500ch, nnaida8 ~600ch, nnaida11 ~120ch.</p> <p> Update response from Patrick:-</p> <p>Please see posting number 39 for ideas to improve noise and possible reasons why some FEE64 are quieter than others.</p> <p>I think the SYNC problem is likely due to the version of VHDL perhaps not including the flush of buffers and with the widely different data rates. 224k against 3k. </p> <p>This should improve with the VHDL update as I think the flush system is more efficient.</p> <p> </p> <p> </p>
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