AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
AIDA
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Sat Mar 29 11:15:23 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p> The Fast Trigger output of the FEE64 is formed from the OR of the four OR16 signals ( one from each of the ASICs.</p> <p>The logic levels of the OR16 signals are active low in the FPGA and so if the are OR'd together then the output is inactive if any one of the ASICs is inactive.</p> <p>This is a problem when the Fast Trigger is being used by other DAQ systems.</p> <p>A new FPGA program 0x1b4FE01A ( version 26 ) is being compiled.</p> <p>The Fast Trigger output will provide the logic AND of the four OR16 signals which should give the correct signal. This setting is selected by "Setup".</p> <p>The other settings available using the Trigger register are shown below. Note that OR64 is the logic OR of the masked outputs of the ASIC individual Discriminator outputs.</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 0 => </p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC1_data_ready ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 1 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC1_rdo_range and ASIC1_data_ready ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 2 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC2_rdo_range and ASIC2_data_ready ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 3 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= led_trigger(0) ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 4 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= led_raw(0) ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 5 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= chan_reset(0) ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 6 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= force_capture_sync ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 7 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= force_capture ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 8 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC1_OR_16 ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 9 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC2_OR_16 ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 10 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC3_OR_16 ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 11 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC4_OR_16 ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 12 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC4_OR_16 and ASIC3_OR_16 and ASIC2_OR_16 and ASIC1_OR_16;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 13 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= led_trigger(1) ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 14 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= OR64 ;</p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>when 15 =></p> <p><span class="Apple-tab-span" style="white-space:pre"> </span>trigger_hit <= ASIC4_OR_16 or ASIC3_OR_16 or ASIC2_OR_16 or ASIC1_OR_16;</p></td> </tr> </tbody> </table> </p><p> </p>
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