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Entry time:
Mon Sep 22 09:34:37 2014
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<p>While investigating a VHDL conundrum I have noticed that the Mux ADC serial readout clock has a 'FAST' slew rate on ASICs 1&2 and a normal slew rate on ASICs 3&4.</p> <p>Is it possible that the higher slew rate is actually better filtered by the ASIC de-coupling etc than the slower one.</p> <p>Unfortunately I can't try this out yet as the "conundrum" means the VHDL version isn't good enough just yet.</p> <p>Hopefully today.....</p> <p> </p> <p>Patrick</p>
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