Background was measurement
Pulser: NO
DLT: No
Online: 
Start:21:07
Stop:

Comment: V2A8C9 contains now the 10Hz clock signal coming from
the same section of the clock where the 100Hz sync signal is extracted.
It will be there even if we inhibit the pulser signals to the preamps

SYNC pulser is 200Hz because 
the gate generator produces double peaks from the 100Hz clock

v1a6c13-16 had a configuration error (Trigger window to  short) 
It's corrected at 14:55 (2018/10/30) on file 181030_Conf_BrikenFull_LowThrAdj_masterCLK.xlsx .