<p><strong>Merger, Tape server (WS3) checks: DONE</strong>, writing ~1 1273kB/s, refreshing is fine</p>
<p><strong>Leakage current (WS4): 3.46 uA , stable current</strong></p>
<p><strong>DAQ (WS2): temperature checked, </strong></p>
<p><strong> - clock status:</strong></p>
<p>Clock status test result: Passed 5, Failed 0</p>
<p>Understand status as follows<br />
Status bit 3 : firmware PLL that creates clocks from external clock not locked<br />
Status bit 2 : always logic '1'<br />
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br />
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br />
If all these bits are not set then the operation of the firmware is unreliable</p>
<p><strong> - adc calibration:</strong></p>
<p>Calibration test result: Passed 5, Failed 0</p>
<p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p>
<p> - <strong>white rabbit check:</strong></p>
<p> Base Current Difference<br />
aida01 fault 0xc228 : 0xc272 : 74 <br />
aida02 fault 0x5e98 : 0x5edf : 71 <br />
aida03 fault 0x92d3 : 0x931d : 74 <br />
aida04 fault 0x7a92 : 0x7adc : 74 <br />
aida05 fault 0xedc0 : 0xedcc : 12 <br />
White Rabbit error counter test result: Passed 0, Failed 5</p>
<p>Understand the status reports as follows:-<br />
Status bit 3 : White Rabbit decoder detected an error in the received data<br />
Status bit 2 : Firmware registered WR error, no reload of Timestamp<br />
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p>
<p><strong>DAQ (WS2): everything ok</strong></p>
<p><strong>Online monitoring (WS 5): done</strong></p> |