Michael is modifying the settings of the electron cooler --> changed beam from bunched to coasting

Merger, Tape server (WS3) checks: DONE, writing ~1036 kB/s, refreshing is fine

Leakage current (WS4): 3.46 uA , stable current

DAQ (WS2): temperature checked,

     - clock status:

Clock status test result: Passed 5, Failed 0

Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable

     -  adc calibration:

Calibration test result: Passed 5, Failed 0

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

   - white rabbit check:

     Base         Current     Difference
aida01 fault      0xc228 :      0xc274 :      76  
aida02 fault      0x5e98 :      0x5ee0 :      72  
aida03 fault      0x92d3 :      0x931f :      76  
aida04 fault      0x7a92 :      0x7ade :      76  
aida05 fault      0xedc0 :      0xedcc :      12  
White Rabbit error counter test result: Passed 0, Failed 5

Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR

DAQ (WS2): everything ok

Online monitoring (WS 5): done;