AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
CARME
Draft saved at 00:00:00
Fields marked with
*
are required
Entry time:
Mon Jan 29 08:52:07 2024
Author
*
:
Subject
*
:
09.50 CARME IE514 5.1e-11 mbar ( ambient temperature 16 deg C ) 10.24 DSSD bias OK - attachment 1 10.40 MACB configuration 1 2 3 4 5 mode 0x3 0x3 0x3 0x3 0x3 from VETAR2 from 1 from 1 from 1 from 1 to 2 aida01 aida05 aida09 aida13 to 3 : : : : to 4 : : : : to 5 aida04 aida08 aida12 aida16 WR emulator cables connected to MACB #1 rear panel DAQ reset and DAQ setup between each test below - the FEE64s were NOT power cycled between tests Per https://elog.ph.ed.ac.uk/CARME/478 test WR connecting/disconnecting HDMI cable from VETAR2 to MACB level 0 input was tested 20.1.24 per https://elog.ph.ed.ac.uk/CARME/477 With VETAR2 abd all MACB mode sttings 0x3 observe same WR issues as previously Noted clock & sync cables from WR emulator were swapped ( pay attention to SMA cables cf. Zybo board *not* NIM module as shown in https://elog.ph.ed.ac.uk/DESPEC/517 ) Change MACB level 0 mode from 0x3 to 0xd - all other MACBs mode 0x3 HDMI cabkle from VETAR2 to MACB level 0 input disconnected System wide checks - global clocks all fail - see attachments 2-5 11.14 Reduce MAC config to MACB level 0 plus one MACB connected to FEE64s aida01-aida4 All MACB modes 0x3 System wide checks aida01-aida04 OK. Same problem observed with WR timestamp for aida01-aida04 See attachments 6-9 11.22 Reduce MAC config to one MACB connected to FEE64s aida01-aida4 MACB mode 0x3 System wide checks aida01-aida04 OK. Same problem observed with WR timestamp for aida01-aida04 See attachments 10-13 11.26 One MACB config using MACB 2 of 5 in NIM bin connected to FEE64s aida01-aida4 MACB mode 0x3 System wide checks aida01-aida04 OK. Same problem observed with WR timestamp for aida01-aida04 See attachments 14-17 11.36 Connect VETAR2 output directly to aida09 System wide checks for aida09 OK.Valid WR timestamp appears to be generated. See attachments 18-20 Check NIM bin with MACBs etc +/-6V, 12V and 24V lines OK 11.42 Connect VETAR2 to MACB 1 of 5 ( mode 0x3 ) Connect aida09 to MACB 1 of 5 Global clock OK. WR decoder status error 0xd reported for aida09. Valid WR timestamp for aida09. See attachments 21-24 11.53 Connect VETAR2 to MACB 1 of 5 ( mode 0x3 ) Connect aida09-aida12 to MACB 1 of 5 Global clock OK. WR decoder status error 0xd reported for aida09-aida12. WR timestamps for aida09-aida12 very different - aida10 might be correct timestamp? See attachments 25-28 11.53 Connect VETAR2 to MACB 2 of 5 ( mode 0x3 ) Connect aida09-aida12 to MACB 2 of 5 Global clock OK. WR decoder status error 0xd reported for aida09-aida12. WR timestamps for aida09-aida12 very different - aida10 & 11 approx correct but 11 has lower timestamp than 10 so probably not quite right See attachments 29-32 15.00 Per https://elog.ph.ed.ac.uk/CARME/478 systematically test 1x MACB configurations to find 'working' MACBs Identify 3x MACB modules which produce sensible WR timestamps - all labelled ' firmware version 04/20 '. The other 5x MACBs are either unlabelled or labelled unknown. MACB configuration now uses 04/20 MACBs for MACBs 1-3 and unlabelled 2xMACBs fpr MACBs 4-5 aida01-aida08 should produce WR timestamps OK Will attempt to update firmwre of 5x MACBs tomorrow pm with NH
Encoding
:
HTML
ELCode
plain
Suppress Email notification
Resubmit as new entry
Attachment 1:
Screenshot_from_2024-01-29_10-24-10.png
Original size: 734x462
Attachment 2:
Screenshot_from_2024-01-29_11-05-18.png
Original size: 3840x1080
Attachment 3:
Screenshot_from_2024-01-29_11-05-49.png
Original size: 3840x1080
Attachment 4:
Screenshot_from_2024-01-29_11-08-15.png
Original size: 1920x1014
Attachment 5:
Screenshot_from_2024-01-29_11-08-41.png
Original size: 1920x1014
Attachment 6:
Screenshot_from_2024-01-29_11-20-44.png
Original size: 1920x1014
Attachment 7:
Screenshot_from_2024-01-29_11-21-07.png
Original size: 1920x1014
Attachment 8:
Screenshot_from_2024-01-29_11-21-29.png
Original size: 1920x1014
Attachment 9:
Screenshot_from_2024-01-29_11-22-00.png
Original size: 1920x1014
Attachment 10:
Screenshot_from_2024-01-29_11-28-20.png
Original size: 1920x1014
Attachment 11:
Screenshot_from_2024-01-29_11-28-40.png
Original size: 1920x1014
Attachment 12:
Screenshot_from_2024-01-29_11-28-52.png
Original size: 1920x1014
Attachment 13:
Screenshot_from_2024-01-29_11-29-26.png
Original size: 1920x1014
Attachment 14:
Screenshot_from_2024-01-29_11-33-16.png
Original size: 1920x1014
Attachment 15:
Screenshot_from_2024-01-29_11-33-30.png
Original size: 1920x1014
Attachment 16:
Screenshot_from_2024-01-29_11-33-43.png
Original size: 1920x1014
Attachment 17:
Screenshot_from_2024-01-29_11-34-15.png
Original size: 1920x1014
Attachment 18:
Screenshot_from_2024-01-29_11-40-51.png
Original size: 1920x1014
Attachment 19:
Screenshot_from_2024-01-29_11-41-12.png
Original size: 1920x1014
Attachment 20:
Screenshot_from_2024-01-29_11-41-59.png
Original size: 1920x1014
Attachment 21:
Screenshot_from_2024-01-29_11-48-20.png
Original size: 1920x1014
Attachment 22:
Screenshot_from_2024-01-29_11-48-41.png
Original size: 1920x1014
Attachment 23:
Screenshot_from_2024-01-29_11-48-58.png
Original size: 1920x1014
Attachment 24:
Screenshot_from_2024-01-29_11-49-22.png
Original size: 1920x1014
Attachment 25:
Screenshot_from_2024-01-29_11-57-41.png
Original size: 1920x1014
Attachment 26:
Screenshot_from_2024-01-29_11-58-11.png
Original size: 1920x1014
Attachment 27:
Screenshot_from_2024-01-29_11-58-25.png
Original size: 1920x1014
Attachment 28:
Screenshot_from_2024-01-29_11-59-11.png
Original size: 1920x1014
Attachment 29:
Screenshot_from_2024-01-29_12-05-28.png
Original size: 1920x1014
Attachment 30:
Screenshot_from_2024-01-29_12-05-59.png
Original size: 1920x1014
Attachment 31:
Screenshot_from_2024-01-29_12-06-11.png
Original size: 1920x1014
Attachment 32:
Screenshot_from_2024-01-29_12-07-03.png
Original size: 1920x1014
Attachment 33:
Drop attachments here...
Draft saved at 00:00:00
ELOG V3.1.3-7933898