ELOG CARME

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

CARME

Fields marked with * are required

Entry time:

Wed Feb 7 10:09:14 2024

Author*:

Subject*:

11:00

Changed slow comp threshold to 0x32 (500 keV). Checkloaded.

&nbsp;

Temperature, Statistics fine (see screenshots).

System wide checks fine (see below).

All FEEs pass clock check.

All FEEs pass White Rabbit check.

ADC Calibration check:

FEE64 module aida02 failed 
FEE64 module aida16 failed 
Calibration test result: Passed 14, Failed 2

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

FPGA timestamp error check:

&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida09 fault &nbsp;&nbsp; &nbsp; 0x1 : &nbsp;&nbsp; &nbsp; 0xa : &nbsp;&nbsp; &nbsp; 9 &nbsp; 
FPGA Timestamp error counter test result: Passed 15, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

&nbsp;

Encoding: HTML ELCode plain
Suppress Email notification Resubmit as new entry

Attachment 1: