AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
CARME
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p>11:00</p> <p>Changed slow comp threshold to 0x32 (500 keV). Checkloaded.</p> <p> </p> <p>Temperature, Statistics fine (see screenshots).</p> <p>System wide checks fine (see below).</p> <p>All FEEs pass clock check.</p> <p>All FEEs pass White Rabbit check.</p> <p>ADC Calibration check:</p> <p>FEE64 module aida02 failed<br /> FEE64 module aida16 failed<br /> Calibration test result: Passed 14, Failed 2</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p>FPGA timestamp error check:</p> <p> Base Current Difference<br /> aida09 fault 0x1 : 0xa : 9 <br /> FPGA Timestamp error counter test result: Passed 15, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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