AIDA
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StellarModelling
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Entry time:
Sat Apr 5 00:42:47 2025
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<p>14:50</p> <p> </p> <p>Temperature, Statistics fine (see screenshots).</p> <p>System wide checks fine (see below).</p> <p>All FEEs pass clock check.</p> <p>All FEEs pass White Rabbit check.</p> <p>ADC Calibration check:</p> <p>FEE64 module aida02 failed<br /> FEE64 module aida16 failed<br /> Calibration test result: Passed 14, Failed 2</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p>FPGA timestamp error check:</p> <p> Base Current Difference<br /> aida09 fault 0x1 : 0xa : 9 <br /> FPGA Timestamp error counter test result: Passed 15, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p>16:00 Slow comp thresh lowered to 100 keV in preparation for detector moving. Will have to test systematically what is the highest threshold we can accept</p> <p> </p> <p>17:00 Temps fine. No overnight run.</p> <p> </p> <p> </p> <p> </p>
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