ELOG CARME

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

CARME

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Entry time:

Wed Feb 7 13:50:20 2024

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14:50

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Temperature, Statistics fine (see screenshots).

System wide checks fine (see below).

All FEEs pass clock check.

All FEEs pass White Rabbit check.

ADC Calibration check:

FEE64 module aida02 failed 
FEE64 module aida16 failed 
Calibration test result: Passed 14, Failed 2

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

FPGA timestamp error check:

&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida09 fault &nbsp;&nbsp; &nbsp; 0x1 : &nbsp;&nbsp; &nbsp; 0xa : &nbsp;&nbsp; &nbsp; 9 &nbsp; 
FPGA Timestamp error counter test result: Passed 15, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

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16:00 Slow comp thresh lowered to 100 keV in preparation for detector moving. Will have to test systematically what is the highest threshold we can accept

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17:00 Temps fine. No overnight run.

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