ELOG DESPEC

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:	Sat Mar 29 11:29:03 2025
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> 01.38 DAQ continues OK - file R22_388 > > ASIC settings 2019Dec19-16.19.51 > DSSSD#1 slow comparator 0xa > DSSSD#2 slow comparator 0xa > DSSSD#3 slow comparator 0xd > > BNC PB-5 Pulser > Amplitude1.0V > Attenuation x1 > Frequency 2Hz > tau_d 1ms > - polarity > Delay 250ns, tail pulse > > System wide checks all OK except > > FEE64 module aida07 failed > FEE64 module aida10 failed > Calibration test result: Passed 10, Failed 2 > > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module > > FEE64 Temperatures OK - attachment 1 > Good event statistics OK - attachment 2 > Detector bias & leakage currents OK - attachment 3 > Merger OK - 4.4M data items/s > TapeServer OK - 14Mb/s > > 01.47 no merger server error/warning messages since last check by TD at start of shift 00.00 > > 03.44 merger server error/warning messages since last check e.g. > > MERGE Data Link (30260): bad timestamp 6 3 0xc1bd7e9a 0x0ce9c9c6 0x0000292e0ce9c9c6 0x166b292e0ce9c9c6 0x166b292e0cea5486 > > 03.46 DAQ continues OK - file R22_441 > > System wide checks all OK except > > FEE64 module aida07 failed > FEE64 module aida10 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module > > FPGA timestamp errors > Base Current Difference > aida07 fault 0x1 : 0x2 : 1 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > FEE64 Temperatures OK - attachment 4 > Good event statistics OK - attachment 5 > Detector bias & leakage currents OK - attachment 6 > Merger OK - 4.6M data items/s > TapeServer OK - 15Mb/s > > 02.51 Rate spectra - attachment 7 > > 04.14 p+n junction HEC spectra - attachment 8 > > all spectra zero'd > > 06.22 merger server error/warning messages since last check e.g. > > MERGE Data Link (30265): bad timestamp 11 3 0xc2fc8067 0x02df391e 0x0000324e62df391e 0x166b324e62df391e 0x166b324e643c775e > > 06.23 DAQ continues OK - file R22_508 > > System wide checks all OK except > > FEE64 module aida07 failed > FEE64 module aida10 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module > > White rabbit decoder status > Base Current Difference > aida01 fault 0xe67 : 0xe68 : 1 > aida02 fault 0x6b22 : 0x6b23 : 1 > aida03 fault 0x4c76 : 0x4c77 : 1 > aida04 fault 0x7542 : 0x7543 : 1 > aida05 fault 0x1597 : 0x1599 : 2 > aida06 fault 0xe241 : 0xe243 : 2 > aida07 fault 0x749 : 0x74c : 3 > aida08 fault 0xf854 : 0xf856 : 2 > White Rabbit error counter test result: Passed 4, Failed 8 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > FPGA timestamp errors > > Base Current Difference > aida07 fault 0x1 : 0x2 : 1 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > FEE64 Temperatures OK - attachment 9 > Good event statistics OK - attachment 10 > Detector bias & leakage currents OK - attachment 11 > Merger OK - 4.8M data items/s > TapeServer OK - 14Mb/s Encoding: HTML ELCode plain Suppress Email notification

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