ELOG DESPEC

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:	Sat Mar 29 11:29:40 2025
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> 11.00(Germany) System wide checks okay except: > > FEE64 module aida09 global clocks failed, 6 > Clock status test result: Passed 11, Failed 1 > Understand status as follows > Status bit 3 : firmware PLL that creates clocks from external clock not locked > Status bit 2 : always logic '1' > Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock > Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock > If all these bits are not set then the operation of the firmware is unreliable > > FEE64 module aida07 failed > FEE64 module aida09 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun > calibration for that module > > Statistics (attachment1) > Spectra rates (attachment2) > FEE temps (attachment3) > Leakage currents, written to google sheet (attachment4) > Merger~ 4.9M items/s > Tapeserver ~17MB/s > > In MBS control terminal, connection has been closed intentionally since this morning (file S452f160), > AIDA has been taken out of the timesorter due to the high data rate, buffers were full > AIDA cannot be seen in ucesb or Go4. > > 13.00 System wide checks okay except: > > FEE64 module aida09 global clocks failed, 6 > Clock status test result: Passed 11, Failed 1 > Understand status as follows > Status bit 3 : firmware PLL that creates clocks from external clock not locked > Status bit 2 : always logic '1' > Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock > Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock > If all these bits are not set then the operation of the firmware is unreliable > > FEE64 module aida07 failed > FEE64 module aida09 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun > calibration for that module > > Statistics (attachment5) > Spectra rates (attachment6) > FEE temps (attachment7) > Leakage currents, written to google sheet (attachment8) > Merger~ 5.1M items/s > Tapeserver ~18MB/s > > No timestamp related errors this shift > > 13.37 AIDA MBS control restarted R33_388 > System wide checks same as previous time > > 13.54 beam stopped for access, file R33_396 > > 13.57 seen recent batch of bad timestamp errors in new merger terminal (attachment9) should be around R33_397 > Analysed R33_395, 396, 397, 398 no timewarps > > 14.29 beam back R33_415 > > 14.54 see more bad timestamps in new merger terminal (attachment10) > > 14.55 System wide checks okay except: > > FEE64 module aida09 global clocks failed, 6 > Clock status test result: Passed 11, Failed 1 > Understand status as follows > Status bit 3 : firmware PLL that creates clocks from external clock not locked > Status bit 2 : always logic '1' > Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock > Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock > If all these bits are not set then the operation of the firmware is unreliable > > FEE64 module aida07 failed > FEE64 module aida09 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun > calibration for that module > > Statistics (attachment11) > Spectra rates (attachment12) > FEE temps (attachment13) > Leakage currents, written to google sheet (attachment14) > Merger~ 5.0M items/s > Tapeserver ~17MB/s > > 16.05 AIDA included back into timesorter, AIDA scalers now seen in ucesb, file R33_463 > > 16.15 CA takes over until 18:00 > > 17:11 System wide checks: > > FEE64 module aida09 global clocks failed, 6 > Clock status test result: Passed 11, Failed 1 > Understand status as follows > Status bit 3 : firmware PLL that creates clocks from external clock not locked > Status bit 2 : always logic '1' > Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock > Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock > If all these bits are not set then the operation of the firmware is unreliable > > FEE64 module aida07 failed > FEE64 module aida09 failed > Calibration test result: Passed 10, Failed 2 > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun > calibration for that module > > Base Current Difference > aida07 fault 0xcdd6 : 0xcdd7 : 1 > White Rabbit error counter test result: Passed 11, Failed 1 > > 17:13 FEE64 temps ok - attachment 15 > Statistics ok - attachment 16 > bias and leakage currents ok - attachment 17 Encoding: HTML ELCode plain Suppress Email notification

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ELOG V3.1.4-unknown