21.12 DAQ continues OK - file R33_617
ASIC settings 2019Dec19-16.19.51
DSSSD#1 slow comparator 0xa
DSSSD#2 slow comparator 0xa
DSSSD#3 slow comparator 0xd
BNC PB-5 Pulser
Amplitude1.0V
Attenuation x1
Frequency 2Hz
tau_d 1ms
- polarity
Delay 250ns, tail pulse
21.15 System wide checks
FEE64 module aida09 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida07 failed
FEE64 module aida09 failed
Calibration test result: Passed 10, Failed 2
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x7a58 : 0x7a5a : 2
aida06 fault 0x65bd : 0x65bf : 2
aida07 fault 0xcdd6 : 0xcdda : 4
aida08 fault 0x2ab5 : 0x2ab7 : 2
White Rabbit error counter test result: Passed 8, Failed 4
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida05 fault 0x0 : 0x1 : 1
FPGA Timestamp error counter test result: Passed 11, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 5 4 2 0 1 2 3 3 2 3 11 : 55956
aida02 : 21 4 1 2 2 4 2 2 1 4 7 : 40260
aida03 : 10 4 4 1 6 4 1 3 3 3 6 : 36648
aida04 : 7 2 4 0 2 3 2 4 1 4 15 : 73836
aida05 : 1 3 1 5 4 3 1 2 3 4 6 : 37964
aida06 : 12 3 5 2 1 3 3 3 2 4 7 : 41880
aida07 : 2 4 3 3 4 2 2 4 3 3 6 : 37048
aida08 : 17 13 2 3 2 3 2 3 2 3 7 : 39724
aida09 : 3 7 2 0 1 2 2 3 2 2 7 : 37284
aida10 : 2 5 3 2 2 3 1 3 2 3 7 : 39328
aida11 : 23 18 2 3 2 3 3 2 3 3 6 : 36460
aida12 : 18 7 3 1 1 4 2 2 2 3 7 : 39184
FEE64 Temperatures OK - attachment 1
Good event statistics OK - attachment 2
Detector bias & leakage currents OK - attachment 3
Merger OK - 4.9M data items/s
TapeServer OK - 16Mb/s
All histograms zero'd
21.50 At some point between R33_610 (20.59) and R33_625 (21.30) aida05 stopped producing data (zero good events - see attachment 2)
able to telnet to aida05 - no warnings/error messages in /var/log/messages
DAQ STOP (all except aida05 stopped OK, aida05 remained GOING)
issued aida05 reboot command via telnet command line
DAQ RESET/SETUP/GO (all FEE64s GOING OK except aida05 - zero good events)
21.15 All system wide checks OK *except*
FEE64 module aida09 global clocks failed, 6
Clock status test result: Passed 11, Failed 1
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
FEE64 module aida07 failed
FEE64 module aida09 failed
Calibration test result: Passed 10, Failed 2
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
21.50 aida04 & aida05 statistics for comparison - see attachments 4 & 5 |