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DESPEC

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Message ID: 233     Entry time: Sat Apr 17 07:28:02 2021 Author: LPG, TD  Subject: Saturday 08:00 - 12:00

08:30 CEST HV and leakage currents: elog:233/1 Detector rates: elog:233/2 Temperatures: elog:233/3 WR status: FEE64 module aida06 failed FEE64 module aida07 failed FEE64 module aida10 failed Calibration test result: Passed 9, Failed 3 If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module FPGA status:              Base         Current         Difference aida12 fault      0x0 :      0x1 :      1   FPGA Timestamp error counter test result: Passed 11, Failed 1 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last 09:20 CEST Stats: ok! DB: No faults found ucesb: ok! 09:40 CEST Beam will be stopped in order to increase intensity. Expected to be around 3-4 hours. For now, we still get implants when Beam spill is on. Seems to be fluctuating as they play around. 10:00 CEST Still getting beam, it is fluctuating in intensity Stats: ok! DB: No faults found ucesb: ok! HV and leakage currents: elog:233/4 Detector rates: elog:233/5 Temperatures: elog:233/6 Clock check: ok! ADC calibration: FEE64 module aida06 failed FEE64 module aida07 failed FEE64 module aida10 failed Calibration test result: Passed 9, Failed 3 WR check: ok! FPGA check: Base Current Difference aida12 fault 0x0 : 0x1 : 1 FPGA Timestamp error counter test result: Passed 11, Failed 1 Memory check: ok! 10:40 CEST Stats: ok! DB: No faults found ucesb: ok! 11:00 CEST Stats: ok! DB: No faults found ucesb: ok! 11:30 CEST Stats: ok! DB: No faults found ucesb: ok! 12:00 BST Stats: ok! DB: No faults found ucesb: ok! HV and leakage currents: elog:233/7 Detector rates: elog:233/8 Temperatures: elog:233/9 Clock check: ok! ADC calibration: FEE64 module aida06 failed FEE64 module aida07 failed FEE64 module aida10 failed Calibration test result: Passed 9, Failed 3 WR check: Base Current Difference aida05 fault 0x1a52 : 0x1a53 : 1 aida06 fault 0x4f3e : 0x4f3f : 1 aida07 fault 0x3bcd : 0x3bce : 1 aida08 fault 0xc7c7 : 0xc7c8 : 1 White Rabbit error counter test result: Passed 8, Failed 4 FPGA check: Base Current Difference aida09 fault 0x0 : 0x1 : 1 aida12 fault 0x0 : 0x2 : 2 Memory check: ok!

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ELOG V3.1.4-unknown