AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:26:59 2025
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> Base Current Difference > aida05 fault 0x1a52 : 0x1a53 : 1 > aida06 fault 0x4f3e : 0x4f3f : 1 > aida07 fault 0x3bcd : 0x3bce : 1 > aida08 fault 0xc7c7 : 0xc7c8 : 1 > White Rabbit error counter test result: Passed 8, Failed 4 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > 13:55 CEST > > Statistics : ok elog:234/4 > Temp : ok elog:234/5 > Bias : ok elog:234/6 > ucesb : ok > DB: No faults found > > ADC Calibration check: > FEE64 module aida06 failed > FEE64 module aida07 failed > FEE64 module aida10 failed > Calibration test result: Passed 9, Failed 3 > > If any modules fail calibration , check the clock status and open the FADC Align and > Control browser page to rerun calibration for that module > > White Rabbit Check: > Base Current Difference > aida05 fault 0x1a52 : 0x1a53 : 1 > aida06 fault 0x4f3e : 0x4f3f : 1 > aida07 fault 0x3bcd : 0x3bcf : 2 > aida08 fault 0xc7c7 : 0xc7c8 : 1 > White Rabbit error counter test result: Passed 8, Failed 4 > > FPGA check: > Base Current Difference > aida09 fault 0x0 : 0x1 : 1 > aida12 fault 0x0 : 0x2 : 2 > FPGA Timestamp error counter test result: Passed 10, Failed 2 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 14:05 no beam > 14:10 beam back > 14:15 no beam, beam current being optimised, going to thicker degrader when beam returns > > > 14:37 CEST > > Statistics : ok > Temp : ok > Bias : ok (ch3 now over 6uA) > ucesb : ok > DB: No faults found > > 15:03 CEST > > Statistics : ok > Temp : ok > Bias : ok > ucesb : ok > DB: No faults found > > 15:31 CEST > > Statistics : ok > Temp : ok > Bias : ok > ucesb : ok > DB: No faults found > > 15:50 > > Statistics : ok elog:234/7 > Temp : ok elog:234/8 > Bias : ok elog:234/9 > ucesb : ok elog:234/10 > DB: No faults found > > ADC Calibration check: > FEE64 module aida06 failed > FEE64 module aida07 failed > FEE64 module aida10 failed > Calibration test result: Passed 9, Failed 3 > > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module > > White Rabbit Check: > Base Current Difference > aida05 fault 0x1a52 : 0x1a53 : 1 > aida06 fault 0x4f3e : 0x4f3f : 1 > aida07 fault 0x3bcd : 0x3bcf : 2 > aida08 fault 0xc7c7 : 0xc7c8 : 1 > White Rabbit error counter test result: Passed 8, Failed 4 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > FPGA check: > Base Current Difference > aida09 fault 0x0 : 0x1 : 1 > aida12 fault 0x0 : 0x2 : 2 > FPGA Timestamp error counter test result: Passed 10, Failed 2 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last
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ELOG V3.1.4-unknown