AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:27:39 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p>02:01 Beam has stopped at 01:37 and returend at 01:43 for few min and then stopped again and not knowen how it will take until it is back</p> <p>AIDA scalers attached 1</p> <p>statistic attached 2</p> <p>temretuer attached 3</p> <p>bias attached 4</p> <p>Clock check ok</p> <p>ADC check :</p> <p>FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida10 failed<br /> Calibration test result: Passed 9, Failed 3</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p><br /> Base Current Difference<br /> aida05 fault 0x1a52 : 0x1a55 : 3 <br /> aida06 fault 0x4f3e : 0x4f41 : 3 <br /> aida07 fault 0x3bcd : 0x3bea : 29 <br /> aida08 fault 0xc7c7 : 0xc7ca : 3 <br /> White Rabbit error counter test result: Passed 8, Failed 4</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida09 fault 0x0 : 0x1 : 1 <br /> aida12 fault 0x0 : 0x9 : 9 <br /> FPGA Timestamp error counter test result: Passed 10, Failed 2<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 32 8 3 1 0 3 1 3 3 3 6 : 36240<br /> aida02 : 11 7 9 3 1 2 2 4 2 3 6 : 35988<br /> aida03 : 32 4 13 5 5 4 3 3 2 3 6 : 36432<br /> aida04 : 26 7 6 1 2 3 2 4 2 3 6 : 36128<br /> aida05 : 18 8 8 7 4 2 2 2 2 4 6 : 37352<br /> aida06 : 24 11 3 1 2 5 1 3 3 3 6 : 36616<br /> aida07 : 14 5 3 3 3 2 3 2 4 3 6 : 37296<br /> aida08 : 21 7 1 5 0 1 2 3 3 3 6 : 36284<br /> aida09 : 0 7 1 1 1 3 2 2 3 3 6 : 35880<br /> aida10 : 22 5 3 4 1 2 2 2 3 3 6 : 35952<br /> aida11 : 4 3 1 1 2 2 3 3 2 3 6 : 35544<br /> aida12 : 22 10 5 4 4 4 1 3 3 3 6 : 36728</p> <p> </p> <p>02:19 beam is back</p> <p>03:58 The beam has not been stable yet</p> <p> The rate reach 1.5 kHz, they will contact FRS team to lower the intensity of the beam</p> <p> </p> <p>AIDA scalers attached 8</p> <p>statistic attached 7</p> <p>temretuer attached 6</p> <p>bias attached 5</p> <p> </p> <p> <br /> FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida10 failed<br /> Calibration test result: Passed 9, Failed 3</p> <p> </p> <p> </p> <p> </p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> <br /> Base Current Difference<br /> aida05 fault 0x1a52 : 0x1a55 : 3 <br /> aida06 fault 0x4f3e : 0x4f41 : 3 <br /> aida07 fault 0x3bcd : 0x3beb : 30 <br /> aida08 fault 0xc7c7 : 0xc7ca : 3 <br /> White Rabbit error counter test result: Passed 8, Failed 4</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida09 fault 0x0 : 0x1 : 1 <br /> aida12 fault 0x0 : 0x9 : 9 <br /> FPGA Timestamp error counter test result: Passed 10, Failed 2<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 21 8 6 2 1 2 1 3 3 3 6 : 36212<br /> aida02 : 24 14 14 2 1 2 2 4 2 3 6 : 36144<br /> aida03 : 31 5 10 5 5 4 2 3 2 3 6 : 36132<br /> aida04 : 12 11 12 2 2 2 3 4 2 3 6 : 36360<br /> aida05 : 23 8 5 7 4 2 2 2 2 4 6 : 37324<br /> aida06 : 21 14 14 1 3 5 1 3 3 3 6 : 36868<br /> aida07 : 15 9 5 0 3 2 3 2 4 3 6 : 37268<br /> aida08 : 21 11 10 3 0 1 2 3 3 3 6 : 36396<br /> aida09 : 5 7 5 1 1 3 1 3 3 3 6 : 36220<br /> aida10 : 15 13 12 3 2 1 2 2 3 3 6 : 36036<br /> aida11 : 13 10 1 0 2 2 2 4 2 3 6 : 35860<br /> aida12 : 29 5 4 5 5 3 1 3 3 3 6 : 36668</p> <p> </p> <p>05: 07 The rate was a bout 1500 and 2000, we contacted Oscar he said (if it's just bursts it should be ok), so they decided to do nothing.</p> <p> </p> <p>06:26 </p> <p>AIDA scalers attached 9</p> <p>statistic attached 10</p> <p>temretuer attached 11</p> <p>bias attached 12</p> <p> </p> <p>Clock status test result: Passed 12, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1'<br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> </p> <p>FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida10 failed<br /> Calibration test result: Passed 9, Failed 3</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> Base Current Difference<br /> aida01 fault 0x7685 : 0x7686 : 1 <br /> aida02 fault 0x941c : 0x941d : 1 <br /> aida03 fault 0x7cd6 : 0x7cd7 : 1 <br /> aida04 fault 0xb86c : 0xb86d : 1 <br /> aida05 fault 0x1a52 : 0x1a59 : 7 <br /> aida06 fault 0x4f3e : 0x4f45 : 7 <br /> aida07 fault 0x3bcd : 0x3bf9 : 44 <br /> aida08 fault 0xc7c7 : 0xc7ce : 7 <br /> aida09 fault 0xb33a : 0xb33b : 1 <br /> White Rabbit error counter test result: Passed 3, Failed 9</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> Base Current Difference<br /> aida09 fault 0x0 : 0x1 : 1 <br /> aida12 fault 0x0 : 0xa : 10 <br /> FPGA Timestamp error counter test result: Passed 10, Failed 2<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p>Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 17 12 6 2 1 2 1 3 3 3 6 : 36228<br /> aida02 : 19 11 12 3 2 2 2 4 2 3 6 : 36164<br /> aida03 : 25 8 12 5 4 4 3 3 2 3 6 : 36356<br /> aida04 : 22 19 11 3 1 2 3 4 2 3 6 : 36416<br /> aida05 : 35 6 5 6 3 2 2 2 3 3 6 : 36236<br /> aida06 : 12 11 11 2 3 4 1 3 3 3 6 : 36664<br /> aida07 : 18 6 2 1 3 2 3 2 3 3 6 : 36216<br /> aida08 : 27 10 8 3 0 1 2 3 3 3 6 : 36380<br /> aida09 : 18 6 6 1 0 2 2 2 3 3 6 : 35832<br /> aida10 : 3 14 10 3 1 1 2 3 3 3 6 : 36412<br /> aida11 : 1 3 2 0 2 2 2 4 2 3 6 : 35772<br /> aida12 : 0 5 6 3 3 4 1 3 3 3 6 : 36520</p> <p> </p> <p>07:57 The beam stopped and they said there is a water leak !</p> <p> </p> <p> </p> <p> </p> <p> </p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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