AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:30:11 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p><strong>07:47</strong><br /> <br /> <br /> Clock status test result: Passed 12, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1' <br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> <br /> FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida10 failed<br /> Calibration test result: Passed 9, Failed 3</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> <br /> Base Current Difference<br /> aida01 fault 0x7686 : 0x768a : 4 <br /> aida02 fault 0x941d : 0x9421 : 4 <br /> aida03 fault 0x7cd7 : 0x7cdb : 4 <br /> aida04 fault 0xb86d : 0xb871 : 4 <br /> aida05 fault 0x1a59 : 0x1a61 : 8 <br /> aida06 fault 0x4f45 : 0x4f4d : 8 <br /> aida07 fault 0x3bfc : 0x3c46 : 74 <br /> aida08 fault 0xc7ce : 0xc7d5 : 7 <br /> aida09 fault 0xb33b : 0xb33c : 1 <br /> White Rabbit error counter test result: Passed 3, Failed 9</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida09 fault 0x1 : 0x2 : 1 <br /> aida12 fault 0xa : 0x35 : 43 <br /> FPGA Timestamp error counter test result: Passed 10, Failed 2<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 19 18 10 7 1 3 2 4 2 3 6 : 36380<br /> aida02 : 11 15 5 3 2 3 2 3 1 4 6 : 36692<br /> aida03 : 15 11 13 3 4 3 3 3 2 3 6 : 36164<br /> aida04 : 22 14 20 5 1 3 4 3 2 3 6 : 36456<br /> aida05 : 7 7 5 2 1 2 3 4 2 3 6 : 36132<br /> aida06 : 21 14 6 2 3 3 1 2 2 4 6 : 37028<br /> aida07 : 11 8 7 4 2 3 2 2 4 3 6 : 37212<br /> aida08 : 18 10 7 5 3 1 4 3 2 3 6 : 36072<br /> aida09 : 24 23 18 3 2 3 2 4 2 3 6 : 36504<br /> aida10 : 6 19 5 2 2 2 2 3 2 3 6 : 35520<br /> aida11 : 22 15 7 2 1 3 2 3 2 3 6 : 35648<br /> aida12 : 35 13 8 2 5 3 1 3 3 3 6 : 36724</p> <p> </p> <p>At <strong>8:30</strong> DAQ and Temperature Scan stopped working properly.</p> <p> </p> <p> </p> <p><strong>11:00</strong></p> <p>It was noted that at the time that AIDA dropped out ~8:30 the beam also dropped out. It seems a bit of a coincidence</p> <p>TD and MS powercycled the FEEs after the first crash and restarted MIDAS but not the merger. This recovered the FEEs but did not re-establish the links between the FEEs and the Merger.</p> <p>Another powercycle was performed this time with a full reset of the merger and the links were restored. Upon restoring there was a large amount of noise in across all FEEs on average a 50% increase across all FEEs but in DSSD a factor of 4-6 increase was common.</p> <p>In the waveforms large 100kHz transiets could be seen - <strong>attachment 4</strong></p> <p>A further power-cycle was performed by OH. The rates following this powercycle are better than just before the power cycle but have not recovered to pre-glitch levels.</p> <p>The waveforms here are much improved though - <strong>attachment 5 and 6</strong></p> <p> </p> <p> </p> <p><strong>11:45</strong></p> <p>FEE64 module aida09 global clocks failed, 6<br /> Clock status test result: Passed 11, Failed 1</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1' <br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> </p> <p> </p> <p>FEE64 module aida01 failed<br /> FEE64 module aida02 failed<br /> FEE64 module aida03 failed<br /> FEE64 module aida04 failed<br /> FEE64 module aida05 failed<br /> FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida08 failed<br /> FEE64 module aida09 failed<br /> FEE64 module aida10 failed<br /> FEE64 module aida11 failed<br /> FEE64 module aida12 failed<br /> Calibration test result: Passed 0, Failed 12</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> </p> <p> <br /> White Rabbit error counter test result: Passed 12, Failed 0</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p>FPGA Timestamp error counter test result: Passed 12, Failed 0<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 1 2 2 1 2 4 2 4 2 3 7 : 40148<br /> aida02 : 5 4 2 2 1 2 2 3 2 3 7 : 39380<br /> aida03 : 3 2 1 1 1 3 1 4 2 3 7 : 39692<br /> aida04 : 4 2 1 0 1 3 3 3 2 3 7 : 39664<br /> aida05 : 2 7 2 0 2 2 3 4 2 3 7 : 40160<br /> aida06 : 2 3 2 2 2 2 1 3 3 3 7 : 40192<br /> aida07 : 23 7 2 0 0 3 2 4 2 3 7 : 39988<br /> aida08 : 23 11 4 0 1 3 1 4 2 3 7 : 39860<br /> aida09 : 1 3 1 1 2 4 1 3 1 4 7 : 40396<br /> aida10 : 1 3 3 1 1 4 1 2 3 3 7 : 39852<br /> aida11 : 3 0 2 3 1 2 3 2 2 3 7 : 39116<br /> aida12 : 5 8 0 3 1 4 2 3 2 3 7 : 39668</p> <p> </p> <p> </p> <p> </p> <p> </p> <p> </p> <p> </p> <p> </p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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