AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:29:48 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p><strong>8:00</strong><br /> <br /> <br /> </p> <p> <br /> Clock status test result: Passed 12, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1' <br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable<br /> </p> <p>FEE64 module aida01 failed<br /> FEE64 module aida02 failed<br /> FEE64 module aida03 failed<br /> FEE64 module aida04 failed<br /> FEE64 module aida05 failed<br /> FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida08 failed<br /> FEE64 module aida09 failed<br /> FEE64 module aida10 failed<br /> FEE64 module aida11 failed<br /> FEE64 module aida12 failed<br /> Calibration test result: Passed 0, Failed 12</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> <br /> White Rabbit error counter test result: Passed 12, Failed 0</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> Base Current Difference<br /> aida12 fault 0x0 : 0x15 : 21 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 19 6 7 2 2 4 3 2 2 3 7 : 39596<br /> aida02 : 25 3 2 1 1 3 2 3 2 3 7 : 39548<br /> aida03 : 28 5 3 1 2 2 2 3 2 3 7 : 39528<br /> aida04 : 27 6 2 2 2 4 2 4 2 3 7 : 40316<br /> aida05 : 9 9 4 3 1 3 2 3 3 3 7 : 40652<br /> aida06 : 21 7 6 1 2 2 4 2 2 3 7 : 39564<br /> aida07 : 20 7 5 0 1 2 2 3 2 3 7 : 39448<br /> aida08 : 21 5 4 1 1 2 3 3 2 3 7 : 39708<br /> aida09 : 1 3 1 3 0 2 1 4 2 3 7 : 39564<br /> aida10 : 20 6 3 2 1 2 3 3 2 3 7 : 39728<br /> aida11 : 18 4 2 1 2 2 2 2 2 3 7 : 38952<br /> aida12 : 19 8 7 1 1 2 3 3 2 3 7 : 39772</p> <p> </p> <p>From the merger statistics during the night there have been 1355757 TS errors in aida12. Corrigan said they have been quiet since around 3am though.</p> <p><br /> <br /> <strong>10:00</strong><br /> <br /> Clock status test result: Passed 12, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1' <br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> </p> <p> <br /> FEE64 module aida01 failed<br /> FEE64 module aida02 failed<br /> FEE64 module aida03 failed<br /> FEE64 module aida04 failed<br /> FEE64 module aida06 failed<br /> FEE64 module aida07 failed<br /> FEE64 module aida08 failed<br /> FEE64 module aida09 failed<br /> FEE64 module aida10 failed<br /> FEE64 module aida11 failed<br /> FEE64 module aida12 failed<br /> Calibration test result: Passed 1, Failed 11</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> <br /> White Rabbit error counter test result: Passed 12, Failed 0</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida12 fault 0x0 : 0x15 : 21 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 15 7 6 2 1 4 3 2 2 3 7 : 39508<br /> aida02 : 1 2 1 0 1 2 2 4 2 3 7 : 39780<br /> aida03 : 23 8 2 0 1 3 2 3 2 3 7 : 39548<br /> aida04 : 23 9 1 2 3 3 2 4 2 3 7 : 40244<br /> aida05 : 14 7 2 2 4 3 2 3 1 4 7 : 40784<br /> aida06 : 18 5 5 2 2 2 3 3 2 3 7 : 39808<br /> aida07 : 27 4 3 2 2 3 3 2 2 3 7 : 39420<br /> aida08 : 23 6 3 2 2 2 3 3 2 3 7 : 39804<br /> aida09 : 18 4 6 3 2 4 3 2 2 3 7 : 39592<br /> aida10 : 6 9 5 3 2 3 2 3 2 3 7 : 39696<br /> aida11 : 16 4 1 2 3 4 1 3 2 3 7 : 39536<br /> aida12 : 18 5 7 1 0 3 3 3 2 3 7 : 39808</p> <p> </p> <p><strong>10:22</strong></p> <p>NH Noticed that the ASIC clocks had not been synchronised following the last AIDA restart. - attachment 7<br /> As the beam is having issues they are not currently recording<br /> I have now synchronised the ASIC clocks.<br /> All ADC are now calibrated</p> <p> </p> <p><strong>11:06</strong></p> <p>Used the beam off time to change the drive writing to. Now writing to /media/ThirdDrive/TapeData/S460/R50</p> <p><strong>11:10</strong></p> <p>Beam is back they will start writing to file again<br /> <br /> <br /> <strong>12:00</strong></p> <p> <br /> Clock status test result: Passed 12, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1' <br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> </p> <p> <br /> Calibration test result: Passed 12, Failed 0</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> </p> <p> <br /> White Rabbit error counter test result: Passed 12, Failed 0</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida12 fault 0x0 : 0x17 : 23 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 20 5 5 1 1 4 2 3 2 3 7 : 39720<br /> aida02 : 16 8 4 1 0 2 1 4 2 3 7 : 39648<br /> aida03 : 9 7 3 2 3 3 2 3 2 3 7 : 39692<br /> aida04 : 8 7 5 2 3 5 3 2 2 3 7 : 39720<br /> aida05 : 20 5 3 4 2 3 3 3 2 3 7 : 39976<br /> aida06 : 25 8 0 3 1 2 3 3 2 3 7 : 39748<br /> aida07 : 24 8 4 2 3 3 2 3 2 3 7 : 39776<br /> aida08 : 22 9 0 2 2 2 3 3 2 3 7 : 39776<br /> aida09 : 1 4 4 3 2 3 2 3 2 3 7 : 39620<br /> aida10 : 13 4 4 3 2 3 1 3 2 3 7 : 39412<br /> aida11 : 2 3 1 1 3 4 2 2 2 3 7 : 39184<br /> aida12 : 16 10 7 2 1 3 1 3 2 3 7 : 39424</p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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