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AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:

Wed Apr 21 15:01:14 2021

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16:30 
 
All System checks okay, except for:

FPGA Timestamp error:

&nbsp;&nbsp;&nbsp; 
&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida12 fault &nbsp;&nbsp; &nbsp; 0x0 : &nbsp;&nbsp; &nbsp; 0x1b : &nbsp;&nbsp; &nbsp; 27 &nbsp; 
FPGA Timestamp error counter test result: Passed 11, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

&nbsp;

Temperature Checks: See attachment 1

Statistics Checks: See attachment 2

Bias &amp; Leakage Currents: See attachment 3

&nbsp;

18:09

All system checks okay, except for: 
 
FPGA Timestamp error:

&nbsp;&nbsp;&nbsp; 
&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida12 fault &nbsp;&nbsp; &nbsp; 0x0 : &nbsp;&nbsp; &nbsp; 0x1d : &nbsp;&nbsp; &nbsp; 29 &nbsp; 
FPGA Timestamp error counter test result: Passed 11, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

&nbsp;

Temperature checks: See attachment 4

Statistics Checks: See attachment 5

Bias &amp; Leakage Currents: See attachment 6

&nbsp;

19:40

All system checks okay, except for: 
 
FPGA Timestamp error:

&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida12 fault &nbsp;&nbsp; &nbsp; 0x0 : &nbsp;&nbsp; &nbsp; 0x1d : &nbsp;&nbsp; &nbsp; 29 &nbsp; 
FPGA Timestamp error counter test result: Passed 11, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

Temperature checks: See attachment 7

Statistics Checks: See attachment 8

Bias &amp; Leakage Currents: See attachment 9

&nbsp;

*Beam being tuned to another experiment (R3B) - all DSSD implants fluctuating back and forth to 0 Hz for around the last hour or so*

22:30

General check

Rates, Voltages, Temperatures, Ucesb are attached 10,11,12,13

Its been noticed that aida04 temp. is incresing to about 65 (red), still below 70.

the system wide check are all ok except FPGA

&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida12 fault &nbsp;&nbsp; &nbsp; 0x0 : &nbsp;&nbsp; &nbsp; 0x1d : &nbsp;&nbsp; &nbsp; 29 &nbsp; 
FPGA Timestamp error counter test result: Passed 11, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

&nbsp;

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