AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:26:38 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p><strong>16:30</strong><br /> <br /> All System checks okay, except for:</p> <p>FPGA Timestamp error:</p> <p> <br /> Base Current Difference<br /> aida12 fault 0x0 : 0x1b : 27 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p>Temperature Checks: See attachment 1</p> <p>Statistics Checks: See attachment 2</p> <p>Bias & Leakage Currents: See attachment 3</p> <p> </p> <p><strong>18:09 </strong></p> <p>All system checks okay, except for:<br /> <br /> FPGA Timestamp error:</p> <p> <br /> Base Current Difference<br /> aida12 fault 0x0 : 0x1d : 29 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p> <p>Temperature checks: See attachment 4</p> <p>Statistics Checks: See attachment 5</p> <p>Bias & Leakage Currents: See attachment 6</p> <p> </p> <p><strong>19:40</strong></p> <p>All system checks okay, except for:<br /> <br /> FPGA Timestamp error:</p> <p> Base Current Difference<br /> aida12 fault 0x0 : 0x1d : 29 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p>Temperature checks: See attachment 7</p> <p>Statistics Checks: See attachment 8</p> <p>Bias & Leakage Currents: See attachment 9</p> <p> </p> <p>*Beam being tuned to another experiment (R3B) - all DSSD implants fluctuating back and forth to 0 Hz for around the last hour or so*</p> <p><strong>22:30</strong></p> <p>General check</p> <p>Rates, Voltages, Temperatures, Ucesb are attached 10,11,12,13</p> <p>Its been noticed that aida04 temp. is incresing to about 65 (red), still below 70.</p> <p>the system wide check are all ok except FPGA</p> <p><br /> Base Current Difference<br /> aida12 fault 0x0 : 0x1d : 29 <br /> FPGA Timestamp error counter test result: Passed 11, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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