ELOG DESPEC

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:	Sat Mar 29 11:28:47 2025
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> 00:07 stats/ucesb/DB checks all ok > > 00:30 all system wide checks ok except fpga errors > > Base Current Difference > aida12 fault 0x0 : 0x1f : 31 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > statistics ok - attachment 1 > > temperatures ok - attachment 2 > > detector bias / leakage currents ok - attachment 3 > > no error messages in DB terminal & ucesb ok - attachment 4 > > 01:00 stats/ucesb/DB checks all ok > > 01:30 stats/ucesb/DB checks all ok > > 01:53 issues with beam dropping in and out - ESR working to stabilise this > > 02:00 stats/ucesb/DB checks all ok > > 02:09 beam back in a stable state > > 02:30 all system wide checks ok except fpga errors > > Base Current Difference > aida12 fault 0x0 : 0x29 : 41 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 02:33 statistics ok - attachment 5 > > temperatures ok - attachment 6 > > detector bias / leakage currents ok - attachment 7 > > no error messages in DB terminal & ucesb ok - attachment 8 > > 02:45 beam off - potentially serious issue, awaiting update from FRS > > 03:00 significant issues with UNILAC, beam not expected back for a while > > 03:05 stats/ucesb/DB checks all ok > > 03:32 stats/ucesb/DB checks all ok > > 03:55 beam is back > > 04:00 stats/ucesb/DB checks all ok > > 04:30 all system wide checks ok except fpga errors > > Base Current Difference > aida12 fault 0x0 : 0x2b : 43 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 04:32 statistics ok - attachment 9 > > temperatures ok - attachment 10 > > detector bias / leakage currents ok - attachment 11 > > no error messages in DB terminal & ucesb ok - attachment 12 > > 05:00 stats/ucesb/DB checks all ok > > 05:30 stats/ucesb/DB checks all ok > > 06:00 stats/ucesb/DB checks all ok > > 06:30 all system wide checks ok except fpga errors > > Base Current Difference > aida12 fault 0x0 : 0x34 : 52 > FPGA Timestamp error counter test result: Passed 11, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 06:32 temperatures ok - attachment 13 > > statistics ok - attachment 14 > > detector bias / leakage currents ok - attachment 15 > > no error messages in DB terminal & ucesb ok - attachment 16 > > 07:00 stats/ucesb/DB checks all ok > > 07:30 stats/ucesb/DB checks all ok > > 07:59 stats/ucesb/DB checks all ok > > > > Encoding: HTML ELCode plain Suppress Email notification

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ELOG V3.1.4-unknown