AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sun Mar 30 09:18:26 2025
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> 11.05 All system wide checks OK *except* > WR > > Base Current Difference > aida01 fault 0xc960 : 0xc971 : 17 > aida02 fault 0x8bbf : 0x8bd0 : 17 > aida03 fault 0xae9e : 0xaeaf : 17 > aida04 fault 0x6e3 : 0x6f4 : 17 > aida05 fault 0x31a4 : 0x31bd : 25 > aida05 : WR status 0x10 > aida06 fault 0x22ea : 0x2303 : 25 > aida07 fault 0x438f : 0x43a8 : 25 > aida08 fault 0x61ed : 0x6206 : 25 > aida09 fault 0x1c32 : 0x1c40 : 14 > aida10 fault 0x9332 : 0x933f : 13 > aida11 fault 0x227b : 0x2288 : 13 > aida12 fault 0xb2fc : 0xb309 : 13 > White Rabbit error counter test result: Passed 0, Failed 12 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > FPGA > > Base Current Difference > aida01 fault 0x0 : 0x1 : 1 > aida02 fault 0x0 : 0x3 : 3 > aida03 fault 0x0 : 0x1 : 1 > aida04 fault 0x0 : 0x2 : 2 > aida06 fault 0x0 : 0x2 : 2 > aida08 fault 0x0 : 0x1 : 1 > aida11 fault 0x0 : 0x3 : 3 > aida12 fault 0x0 : 0x3 : 3 > FPGA Timestamp error counter test result: Passed 4, Failed 8 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > > Looks like a big WR glitch happened at some point (master in issue?) > > Memory > Returned 0 0 0 0 0 0 0 0 0 0 0 0 > Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k > aida01 : 26 20 26 15 3 1 3 2 2 3 4 : 27848 > aida02 : 25 7 1 4 1 4 2 2 3 3 6 : 36204 > aida03 : 30 5 3 3 3 3 1 3 3 3 6 : 36464 > aida04 : 5 10 0 5 2 3 1 3 3 3 6 : 36356 > aida05 : 34 40 16 13 4 3 3 2 3 3 4 : 29160 > aida06 : 16 8 4 2 1 4 1 3 3 3 6 : 36416 > aida07 : 28 23 23 10 4 3 2 4 3 4 3 : 27736 > aida08 : 26 9 3 3 1 3 1 3 3 3 6 : 36352 > aida09 : 54 42 10 17 3 4 3 4 3 3 4 : 30376 > aida10 : 17 5 7 4 3 3 3 3 2 3 6 : 35996 > aida11 : 19 10 11 2 1 1 2 4 2 3 6 : 35916 > aida12 : 82 42 12 7 4 2 3 2 2 3 4 : 27960 > > > Options unchanged from ELOG 284 > > DAQ continues OK but New Merger window has disappeared... clearly still running in background! > > DSSSD leakage currents decreasing as expected > > - > > Plan later today: > > Prepare AIDA Kapton Cables for triple > > install 4 new FEE64s into S4 (13,14,15,16) > > Proposed layout of FEE64s (perspective with beam) in fig 5 > > Cards 9-12 will be moved on Friday when triple is installed > > When ready MAC addressed will be given to OH/TD who will do the PC configuration including: > - Network IP allocation > - MIDAS registration > - Firmware updating > - Checks > > 17.20: > > The four new FEEs have been installed and connected to Ethernet, Power, HDMI and Water > No front-end adapter is connected yet > The MAC addresss are as follows > aida13 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:42: d:15 > aida14 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:42: d: b > aida15 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:ee:10 > aida16 xilinx_lltemac 81c00000.ethernet: MAC address is now d8:80:39:41:f6:ed
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ELOG V3.1.4-unknown