AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Fri May 7 19:47:54 2021
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<p>After tests in the Daresbury T9 system.</p> <p>Disabling the waveform ADCs in an FEE64 which is running with the FPGA over temperature will drop the FPGA temperature by 10 degrees.</p> <p>To disable the ADCs open the <em>Local Control</em> browser window and set the <em>ADC Control</em> register , @2, to 0xFF</p> <p>The easiest way to restart the waveform ADCs correctly is to rerun SETUP from the control window selecting just the FEE that is affected.</p> <p>Alternatively STOP acquisition, set the <em>ADC Control </em> register back to 0 and rerun the calibrate ADCs in the <em>FADC Align and Control</em> browser window.</p> <p> </p>
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