AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:26:13 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p>03:12 <strong>System Check</strong></p> <p>attachment 1 : Current</p> <p>attachment 2 : Temperature</p> <p>attachment 3 : Rates</p> <p> </p> <p> <br /> Clock status test result: Passed 16, Failed 0</p> <p>Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked<br /> Status bit 2 : always logic '1'<br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p> <br /> Calibration test result: Passed 16, Failed 0</p> <p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p> <br /> Base Current Difference<br /> aida05 fault 0x36ca : 0x36cb : 1 <br /> White Rabbit error counter test result: Passed 15, Failed 1</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p> </p> <p> <br /> Base Current Difference<br /> aida13 fault 0xa : 0xf : 5 <br /> FPGA Timestamp error counter test result: Passed 15, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> <br /> Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <br /> Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k<br /> aida01 : 22 5 7 2 1 2 2 3 3 3 6 : 36464<br /> aida02 : 9 8 3 3 1 4 1 2 4 3 6 : 36916<br /> aida03 : 5 2 6 2 0 3 2 3 3 3 6 : 36420<br /> aida04 : 6 5 2 3 4 4 2 3 3 3 6 : 36800<br /> aida05 : 17 6 6 2 2 4 1 3 2 4 6 : 37524<br /> aida06 : 7 12 3 4 3 3 1 3 3 3 6 : 36460<br /> aida07 : 17 11 5 1 3 3 3 2 3 3 6 : 36428<br /> aida08 : 3 5 0 1 4 2 2 4 2 3 6 : 35924<br /> aida09 : 27 6 4 2 0 2 2 2 3 3 6 : 35868<br /> aida10 : 16 11 8 0 2 2 1 3 2 4 6 : 37272<br /> aida11 : 15 2 2 3 1 4 3 4 2 3 6 : 36364<br /> aida12 : 1 6 4 3 1 3 2 4 2 3 6 : 35988<br /> aida13 : 22 14 10 2 4 2 2 4 2 3 6 : 36264<br /> aida14 : 26 10 4 3 2 1 1 3 3 3 6 : 36184<br /> aida15 : 14 2 3 2 2 4 1 2 3 3 6 : 35896<br /> aida16 : 7 5 4 0 2 4 2 3 2 3 6 : 35588</p> <p><strong>06:10 DSSD1 rate high!</strong></p> <p>Attached 4</p> <p>Called OH and he woke up to fix it :)</p> <p>It was a problem with one of the ASIC according to what he says:</p> <p>One of the ASICs HEC was running crazy!. Forced the ASICs to check their settings which brings them to back into line see attachment 9. This done by around 06:35</p> <p> </p> <p><strong>07:03 System check</strong></p> <p>attachment 5 Spectrum rate</p> <p>attachment 6 Voltages</p> <p>attachment 7 Rates</p> <p>attachment 8 Temperature</p> <p>System wide clock are all ok except</p> <p><strong>White rabbit</strong></p> <p> Base Current Difference<br /> aida05 fault 0x36ca : 0x36cb : 1 <br /> White Rabbit error counter test result: Passed 15, Failed 1</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p><strong>FPGA</strong></p> <p> Base Current Difference<br /> aida13 fault 0xa : 0x14 : 10 <br /> FPGA Timestamp error counter test result: Passed 15, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p> </p></td> </tr> </tbody> </table> </p><p> </p>
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