AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Sat Mar 29 11:29:58 2025
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> 00:00 OH Takes over. > PULSER SETTINGS > --------------------------- > Pulse is ON > Positive Tail Pulse > Trigger Source is Internal Clock > Trigger Threshold is 3.5 > Amplitude : 2.0 Volts > Rep Rate : 2.0 hZ > Delay : 250.0 ns > Fall Time : 1 ms > Attenuation : 1 > Display is : Volts > Equivalent keV is : 200.0 > Ramp Start at 0.01 Volts > Ramp Stop at 9.99 Volts > Ramp Start at 1.0 keV > Ramp Stop at 999.0 keV > Ramp Time is 60 seconds > # Ramp Cycles is 1 > > OK > 0x210 > > p+n Thresholds 0xa (100keV) > n+n Threshold 0x20 (320keV) > > 01:00 System wide checks > Clock status ok > ADC calibration fail as expected (Waveforms off) > WR Errors > Base Current Difference > aida01 fault 0xf932 : 0xf933 : 1 > aida02 fault 0x62ec : 0x62ed : 1 > aida03 fault 0x8679 : 0x867a : 1 > aida04 fault 0xf0e4 : 0xf0e5 : 1 > aida05 fault 0x9db8 : 0x9dbf : 7 > aida06 fault 0x7f18 : 0x7f19 : 1 > aida07 fault 0xdd2c : 0xdd2d : 1 > aida08 fault 0x1557 : 0x1558 : 1 > White Rabbit error counter test result: Passed 8, Failed 8 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > FPGA Errors > > Base Current Difference > aida05 fault 0x0 : 0x2 : 2 > FPGA Timestamp error counter test result: Passed 15, Failed 1 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > Statistics ok - attachment 1 > Temp ok - attachment 2 > Bias and leakage current ok - attachment 3 > > 01:42 Comparing the CS of AIDA3 and 4 > Stats have been running for a while (Believe since 5am) > Looking at the counter ratio - attachment 4 > We still have a deadtime of around 14% in FEE4 (Assuming FEE3 has no dead time) > > 01:56 Noticed /media/ThirdDrive was at 97% full > Let DESPEC locals know I would like to use the next run stop to change the directory. > They said they could do it now so they stopped their run. > Changed the symbolic link to /media/1e2.... > Now writing to R4_ > > 03:26 MBS DAQ Stopped as beam stopped > 03:33 Beam back now and DAQ running again > > 04:44 System wide checks as before > Statistics ok - attachment 5 > Temperatures ok - attachment - 7 > Bias and leakage currents ok - attachment 6 > > 05:53 MBS stops run as beam drops > 06:00 MBS started a new run as beam is back > > 07:37 System wide checks clock ok and FPGA as before > WR additional difference on FEE5 > > Base Current Difference > aida01 fault 0xf932 : 0xf933 : 1 > aida02 fault 0x62ec : 0x62ed : 1 > aida03 fault 0x8679 : 0x867a : 1 > aida04 fault 0xf0e4 : 0xf0e5 : 1 > aida05 fault 0x9db8 : 0x9dc0 : 8 > aida06 fault 0x7f18 : 0x7f19 : 1 > aida07 fault 0xdd2c : 0xdd2d : 1 > aida08 fault 0x1557 : 0x1558 : 1 > White Rabbit error counter test result: Passed 8, Failed 8 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > Statistics ok - attachment 8 > Temp ok - attachment 9 > Bias and leakage ok - attachment 10 >
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