0.00 - Taking over from Lewis
00.30 - Rates look ok (fig1), Ran R14_147 through analyser, dead times all good (fig2)
01.00 - Rates look ok (Fig3), Ran R14_153 through analyser, dead times all good (fig4)
01.30 - Rates look ok (Fig5), Ran R14_158 through analyser, dead times all good (fig6)
02.00 - Rates look ok (Fig7), Ran R14_164 through analyser, dead times all good (fig8)
Leakage current ok (fig 9), Temps OK (fig10), UCESB looks ok (fig11)
System Wide Checks:
Clock status test result: Passed 16, Failed 0
Calibration test result: Passed 0, Failed 16
Base Current Difference
aida05 fault 0x4da : 0x4ee : 20
White Rabbit error counter test result: Passed 15, Failed 1
FPGA Timestamp error counter test result: Passed 16, Failed 0
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 43 12 6 4 1 4 2 2 1 3 7 : 38444
aida02 : 21 12 4 4 2 3 3 3 3 3 6 : 36980
aida03 : 23 8 4 2 2 4 2 3 3 3 6 : 36764
aida04 : 34 12 10 5 1 4 1 4 3 3 6 : 37224
aida05 : 18 5 5 1 2 3 2 2 1 3 7 : 38112
aida06 : 40 12 5 7 2 4 2 4 3 3 6 : 37552
aida07 : 40 10 6 2 2 4 2 2 2 2 7 : 37392
aida08 : 19 11 3 3 1 4 3 3 3 3 6 : 36980
aida09 : 43 6 2 4 3 4 3 3 3 3 6 : 37180
aida10 : 32 14 10 3 4 1 2 4 1 3 7 : 39280
aida11 : 40 7 2 5 4 3 1 4 3 3 6 : 37144
aida12 : 37 14 13 2 2 3 2 4 3 3 6 : 37396
aida13 : 18 9 3 1 1 5 3 3 3 3 6 : 37024
aida14 : 36 13 6 4 2 3 2 3 1 3 7 : 38872
aida15 : 32 11 7 4 3 4 2 3 2 4 6 : 38024
aida16 : 26 9 4 1 0 3 1 4 3 3 6 : 36752
02.30 - rates ok (fig 12), Ran R14_170 through analyser, dead times all good (fig13)
03.00 - rates ok (fig 14), Ran R14_175 through analyser, dead times all good (fig15)
03.05 - No beam, problem with SIS, don't know how long will be off
03.14 - Beam is back
03.30 - rates ok (fig 16), Ran R14_180 through analyser, dead times all good (fig17)
04.00 - rates ok (fig 18), Ran R14_186 through analyser, dead times all good (fig19)
Leakage current ok (fig 20), Temps OK (fig21), UCESB looks ok (fig22)
System Wide Checks:
Clock status test result: Passed 16, Failed 0
Calibration test result: Passed 0, Failed 16
Base Current Difference
aida05 fault 0x4da : 0x4f2 : 24
White Rabbit error counter test result: Passed 15, Failed 1
FPGA Timestamp error counter test result: Passed 16, Failed 0
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 26 11 5 6 1 4 2 2 1 3 7 : 38416
aida02 : 16 9 5 4 2 4 2 2 3 3 6 : 36312
aida03 : 9 7 4 4 2 4 2 3 3 3 6 : 36764
aida04 : 36 11 8 4 3 4 1 3 4 3 6 : 37800
aida05 : 20 4 3 2 2 3 2 2 1 3 7 : 38112
aida06 : 22 13 10 7 2 4 3 3 4 3 6 : 38336
aida07 : 28 7 7 2 2 4 2 2 2 2 7 : 37336
aida08 : 2 3 4 4 1 3 2 3 3 3 6 : 36512
aida09 : 40 7 1 4 4 3 3 3 3 3 6 : 37096
aida10 : 26 9 12 2 3 2 2 4 1 3 7 : 39280
aida11 : 30 7 1 5 4 3 1 3 2 4 6 : 37600
aida12 : 15 10 6 4 2 3 2 4 3 3 6 : 37228
aida13 : 1 3 2 1 2 4 3 2 3 3 6 : 36316
aida14 : 34 12 7 4 2 3 2 3 1 3 7 : 38872
aida15 : 18 11 5 3 4 4 2 3 2 4 6 : 37968
aida16 : 22 7 4 2 0 3 1 4 3 3 6 : 36752
04.30 - rates ok (fig23), Ran R14_192 through analyser, dead times all good (fig24)
05.00 - rates ok (fig25), Ran R14_198 through analyser, dead times all good (fig26)
05.30 - Rates ok (Fig27), Ran R14_203 through analyser, dead times all good (fig28)
06.00 - Rates ok (Fig29), Ran R14_203 through analyser, dead times all good (fig30)
Leakage current ok (fig 31), Temps OK (fig32), UCESB looks ok (fig33)
System Wide Checks:
Clock status test result: Passed 16, Failed 0
Calibration test result: Passed 0, Failed 16
Base Current Difference
aida05 fault 0x4da : 0x4f9 : 31
White Rabbit error counter test result: Passed 15, Failed 1
FPGA Timestamp error counter test result: Passed 16, Failed 0
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 16 9 3 7 1 5 1 3 1 3 7 : 38744
aida02 : 18 3 5 2 3 3 3 2 3 3 6 : 36400
aida03 : 21 9 4 2 2 4 2 4 3 3 6 : 37276
aida04 : 32 12 7 3 3 4 1 3 4 3 6 : 37744
aida05 : 12 8 3 2 2 4 2 2 1 3 7 : 38240
aida06 : 28 14 4 8 2 4 3 3 3 3 6 : 37280
aida07 : 40 12 5 2 2 4 1 3 2 2 7 : 37648
aida08 : 13 8 4 4 1 3 2 3 3 3 6 : 36596
aida09 : 35 5 2 4 3 4 2 4 3 3 6 : 37396
aida10 : 6 10 4 1 1 3 2 2 1 3 7 : 38024
aida11 : 41 9 1 4 4 3 2 4 3 3 6 : 37372
aida12 : 29 11 9 4 2 3 2 4 3 3 6 : 37340
aida13 : 24 10 5 1 2 4 3 2 3 3 6 : 36512
aida14 : 34 16 5 4 2 3 2 3 1 3 7 : 38872
aida15 : 42 8 6 2 4 4 2 3 2 4 6 : 38024
aida16 : 8 9 6 1 0 3 1 4 3 3 6 : 36712
06.30 - Rates look ok (Fig34), Ran R14_215 through analyser, dead times all good (fig35)
07.00 - Rates look ok (Fig36), Ran R14_221 through analyser, dead times all good (fig 37)
07.25 - Rates look ok (Fig38), Ran R14_226 through analyser, dead times all good (fig 39) |