ELOG DESPEC

AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

DESPEC

Fields marked with * are required
Entry time:	Sat Mar 29 11:26:50 2025
Author*:
Subject*:
> 16th May 2021 - 00:00 - 08:00 Shift > Author: CA > > 00:15 System wide checks; > > FEE64 module aida06 global clocks failed, 6 > FEE64 module aida09 global clocks failed, 6 > Clock status test result: Passed 14, Failed 2 > > Understand status as follows > Status bit 3 : firmware PLL that creates clocks from external clock not locked > Status bit 2 : always logic '1' > Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock > Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock > If all these bits are not set then the operation of the firmware is unreliable > > FEE64 module aida09 failed > Calibration test result: Passed 15, Failed 1 > > If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module > > Base Current Difference > aida05 fault 0x714c : 0x7154 : 8 > White Rabbit error counter test result: Passed 15, Failed 1 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > Base Current Difference > aida05 fault 0x0 : 0x3 : 3 > aida12 fault 0x0 : 0x3 : 3 > aida13 fault 0x0 : 0x4d : 77 > FPGA Timestamp error counter test result: Passed 13, Failed 3 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k > aida01 : 19 10 3 1 2 3 2 3 2 3 7 : 39660 > aida02 : 29 5 3 1 1 3 2 3 2 3 7 : 39596 > aida03 : 15 7 1 1 2 3 2 3 2 3 7 : 39588 > aida04 : 44 26 19 5 2 4 3 3 2 2 7 : 38608 > aida05 : 20 10 3 0 1 4 2 2 3 3 7 : 40208 > aida06 : 27 6 2 1 2 4 2 4 2 3 7 : 40284 > aida07 : 25 5 3 1 2 3 2 3 2 3 7 : 39644 > aida08 : 23 8 2 3 1 4 2 3 2 3 7 : 39772 > aida09 : 23 10 3 2 3 4 1 3 2 3 7 : 39644 > aida10 : 18 10 3 2 3 2 2 2 2 4 7 : 41160 > aida11 : 16 7 3 2 1 2 2 3 2 3 7 : 39464 > aida12 : 21 4 7 1 3 3 3 3 2 3 7 : 40004 > aida13 : 25 6 3 2 1 3 1 4 2 3 7 : 39876 > aida14 : 20 8 10 1 1 2 2 2 2 4 7 : 41104 > aida15 : 26 6 3 3 0 4 3 2 2 3 7 : 39464 > aida16 : 9 8 2 4 1 3 1 4 2 3 7 : 39876 > > 00:30 Stats ok - 210516_0030_stats.png > Temps ok - 210516_0030_temps.png > Bias ok - 210516_0030_bias.png > > 00:38 analyzer output R7_178 - Deadtime at 7.3% - 210516_R7_178_analysis.txt > > 02:21 system wide checks as above, except; > > Base Current Difference > aida05 fault 0x714c : 0x7159 : 13 > White Rabbit error counter test result: Passed 15, Failed 1 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > Base Current Difference > aida05 fault 0x0 : 0x7 : 7 > aida12 fault 0x0 : 0x3 : 3 > aida13 fault 0x0 : 0x4d : 77 > FPGA Timestamp error counter test result: Passed 13, Failed 3 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 02:28 Stats ok - 210516_0230_stats.png > Temps ok - 210516_0230_temps.png > Bias ok - 210516_0230_bias.png > > 02:33 analyzer output R7_216 - Deadtime at 6.5% - 210516_R7_216_analysis.txt > > 04:36 system wide checks same as above, except; > > Base Current Difference > aida05 fault 0x714c : 0x715c : 16 > White Rabbit error counter test result: Passed 15, Failed 1 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > Base Current Difference > aida05 fault 0x0 : 0x9 : 9 > aida12 fault 0x0 : 0x3 : 3 > aida13 fault 0x0 : 0x4d : 77 > FPGA Timestamp error counter test result: Passed 13, Failed 3 > If any of these counts are reported as in error > The ASIC readout system has detected a timeslip. > That is the timestamp read from the time FIFO is not younger than the last > > 04:37 Stats ok - 210516_0430_stats.png > Temps ok - 210516_0430_temps.png > Bias ok - 210516_0430_bias.png > > 04:44 analyzer output R7_260 - Deadtime at 6.9% - 210516_R7_260_analysis.txt > > 06:38 system wide checks same as before, except; > > Base Current Difference > aida01 fault 0xf294 : 0xf296 : 2 > aida02 fault 0xd8ec : 0xd8ee : 2 > aida03 fault 0xf001 : 0xf003 : 2 > aida04 fault 0xd992 : 0xd994 : 2 > aida05 fault 0x714c : 0x7161 : 21 > aida06 fault 0x5a49 : 0x5a4a : 1 > aida07 fault 0x5aca : 0x5acb : 1 > aida08 fault 0xb92e : 0xb92f : 1 > White Rabbit error counter test result: Passed 8, Failed 8 > > Understand the status reports as follows:- > Status bit 3 : White Rabbit decoder detected an error in the received data > Status bit 2 : Firmware registered WR error, no reload of Timestamp > Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR > > 06:40 Stats ok - 210516_0640_stats.png > Temps ok - 210516_0640_temps.png > Bias ok - 210516_0640_bias.png > > 06:45 analyzer output R7_298 - Deadtime at 5.8% - 210516_R7_298_analysis.txt Encoding: HTML ELCode plain Suppress Email notification

Attachment 1:
Drop attachments here...

ELOG V3.1.4-unknown