AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Entry time:
Wed May 19 11:24:55 2021
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System checks gave 11 passed/1 failed, except for ADC timimgs: 10 passed/2 failed. FEE64 module aida09 global clocks failed, 6 Clock status test result: Passed 11, Failed 1 Understand status as follows Status bit 3 : firmware PLL that creates clocks from external clock not locked Status bit 2 : always logic '1' Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock If all these bits are not set then the operation of the firmware is unreliable FEE64 module aida07 failed FEE64 module aida09 failed Calibration test result: Passed 10, Failed 2 Base Current Difference aida07 fault 0xd052 : 0xd056 : 4 White Rabbit error counter test result: Passed 11, Failed 1 Understand the status reports as follows:- Status bit 3 : White Rabbit decoder detected an error in the received data Status bit 2 : Firmware registered WR error, no reload of Timestamp Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR Base Current Difference aida12 fault 0x0 : 0x16 : 22 FPGA Timestamp error counter test result: Passed 11, Failed 1 If any of these counts are reported as in error The ASIC readout system has detected a timeslip. That is the timestamp read from the time FIFO is not younger than the last If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module Returned 0 0 0 0 0 0 0 0 0 0 0 0 Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k aida01 : 2 6 2 0 5 5 1 2 3 3 6 : 36120 aida02 : 25 10 0 4 3 5 2 3 3 3 6 : 36980 aida03 : 22 12 5 2 1 3 2 3 3 3 6 : 36616 aida04 : 16 3 3 3 4 4 4 2 3 3 6 : 36840 aida05 : 14 5 6 2 3 4 4 2 3 3 6 : 36800 aida06 : 30 10 6 3 3 4 2 3 3 3 6 : 36936 aida07 : 27 11 1 0 0 3 2 3 3 3 6 : 36436 aida08 : 38 7 7 3 3 2 2 3 3 3 6 : 36704 aida09 : 4 6 4 2 4 4 1 4 3 3 6 : 37056 aida10 : 21 10 3 3 1 5 1 3 3 3 6 : 36596 aida11 : 24 8 2 1 4 3 2 4 2 3 6 : 36192 aida12 : 31 12 4 3 5 5 2 2 3 3 6 : 36668 Collecting the file size of each FEE64 Options CONTENTS file to check they are all the same FEE : aida01 => Options file size is 1025 Last changed Mon Apr 19 10:32:22 CEST 2021 FEE : aida02 => Options file size is 1014 Last changed Fri Apr 16 00:56:20 CEST 2021 FEE : aida03 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida04 => Options file size is 1025 Last changed Sat Apr 17 06:07:36 CEST 2021 FEE : aida05 => Options file size is 1025 Last changed Fri Apr 16 00:53:25 CEST 2021 FEE : aida06 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida07 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida08 => Options file size is 1014 Last changed Wed Apr 14 21:52:04 CEST 2021 FEE : aida09 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021 FEE : aida10 => Options file size is 1014 Last changed Wed Apr 14 21:52:06 CEST 2021 FEE : aida11 => Options file size is 1014 Last changed Wed Apr 14 21:52:05 CEST 2021 FEE : aida12 => Options file size is 1025 Last changed Mon Apr 19 09:05:25 CEST 2021 There should be a separate elog note about changing one of the bias voltages. All histograms zeroed at 16:13. 16.20 DAQ continues file NULL/R33_156 aida09 HEC fast comparator 0x2->0x1 DSSSD#3 bias -100->-120V
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ELOG V3.1.4-unknown