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AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:

Sat May 14 17:34:40 2022

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FEE64 module aida09 global clocks failed, 6 
&nbsp;Clock status test result: Passed 13, Failed 1

Understand status as follows 
Status bit 3 : firmware PLL that creates clocks from external clock not locked 
Status bit 2 : always logic &#39;1&#39; 
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock 
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock 
If all these bits are not set then the operation of the firmware is unreliable

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FEE64 module aida02 failed 
FEE64 module aida06 failed 
FEE64 module aida09 failed 
FEE64 module aida10 failed 
FEE64 module aida13 failed 
Calibration test result: Passed 9, Failed 5

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

White Rabbit error counter test result: Passed 14, Failed 0

Understand the status reports as follows:- 
Status bit 3 : White Rabbit decoder detected an error in the received data 
Status bit 2 : Firmware registered WR error, no reload of Timestamp 
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR

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FPGA Timestamp error counter test result: Passed 14, Failed 0 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

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