<p>FEE64 module aida09 global clocks failed, 6<br />
Clock status test result: Passed 13, Failed 1</p>
<p>Understand status as follows<br />
Status bit 3 : firmware PLL that creates clocks from external clock not locked<br />
Status bit 2 : always logic '1'<br />
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br />
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br />
If all these bits are not set then the operation of the firmware is unreliable</p>
<p> </p>
<p>FEE64 module aida02 failed<br />
FEE64 module aida06 failed<br />
FEE64 module aida09 failed<br />
FEE64 module aida10 failed<br />
FEE64 module aida13 failed<br />
Calibration test result: Passed 9, Failed 5</p>
<p>If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p>
<p>White Rabbit error counter test result: Passed 14, Failed 0</p>
<p>Understand the status reports as follows:-<br />
Status bit 3 : White Rabbit decoder detected an error in the received data<br />
Status bit 2 : Firmware registered WR error, no reload of Timestamp<br />
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p>
<p> </p>
<p>FPGA Timestamp error counter test result: Passed 14, Failed 0<br />
If any of these counts are reported as in error<br />
The ASIC readout system has detected a timeslip.<br />
That is the timestamp read from the time FIFO is not younger than the last</p>
<p> </p> |