<p>16:05 - Last checked was at 15:30. (see previous entry. All running smoothly. </p>
<p>Next wide check will be in about an hour.</p>
<p>17:00</p>
<p>Stats -ok - attachment 1</p>
<p>Temperatures ok - attachement 2</p>
<p>Leakage current ok but - attachment 3</p>
<p>ucesb screen-shot - attachment 4</p>
<p>Wide check completed. Nothing different.</p>
<p>WR status decoder status: <br />
Base Current Difference<br />
aida07 fault 0xc53d : 0xc547 : 10 <br />
aida08 fault 0xf1be : 0xf1e9 : 43 <br />
White Rabbit error counter test result: Passed 6, Failed 2</p>
<p>Understand the status reports as follows:-<br />
Status bit 3 : White Rabbit decoder detected an error in the received data<br />
Status bit 2 : Firmware registered WR error, no reload of Timestamp<br />
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p>
<p> </p>
<p>FPGA timestamp:: <br />
Base Current Difference<br />
aida07 fault 0x2a : 0x2c : 2 <br />
FPGA Timestamp error counter test result: Passed 7, Failed 1<br />
If any of these counts are reported as in error<br />
The ASIC readout system has detected a timeslip.<br />
That is the timestamp read from the time FIFO is not younger than the last</p>
<p>Note that the leakage current is ok but has increased since yesterday , See graphana - attachement 5 - Prossibly due to higher beam intensity.</p>
<p> </p>
<p> </p>
<p>19:20 -</p>
<p>Stats ok - attachment 6</p>
<p>Temp ok - attachment 7</p>
<p>Leakage current ok - attachement 8</p>
<p>Wide check completed and same output as above.</p>
<p> </p>
<p>22:00</p>
<p>Stats ok - attachment 9</p>
<p>Temp ok - attachment 10</p>
<p>Leakage current ok - attachement 11</p>
<p>Wide check completed and same output as above.</p>
<p> </p>
<p> </p> |