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AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:

Sun Jun 26 23:04:30 2022

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0:00 Experiment continues to run smoothly. AIDA DAQ has been rather stable. Leakage current has gone up for the past two days in both DSSDs (combination of high-Z and high-intensity beam and external high temperature).

Stats &amp; Temperatures (VIRTEX,PSU, ASICs)&nbsp; all ok.

At 0:30

Stats ok - Attachment 1

Temp ok - Attachement 2

HV-LC -Attachment 3

At 2:20

Stats ok - Attachment 4

Temp ok - Attachement 5

HV-LC -Attachment 6

Wide Checks:

Clock status test result: Passed 8, Failed 0&nbsp;&nbsp;

&nbsp;&nbsp;&nbsp; Understand status as follows 
&nbsp;&nbsp;&nbsp; Status bit 3 : firmware PLL that creates clocks from external clock not locked&nbsp; 
&nbsp;&nbsp;&nbsp; Status bit 2 : always logic &#39;1&#39; 
&nbsp;&nbsp;&nbsp; Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock 
&nbsp;&nbsp;&nbsp; Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock 
&nbsp;&nbsp;&nbsp; If all these bits are not set then the operation of the firmware is unreliable

ADC Calibration (same as before):

&nbsp; &nbsp; FEE64 module aida01 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida02 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida03 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida04 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida05 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida06 failed&nbsp;&nbsp; 
&nbsp;&nbsp;&nbsp; FEE64 module aida07 failed 
&nbsp;&nbsp;&nbsp; FEE64 module aida08 failed 
&nbsp;&nbsp;&nbsp; Calibration test result: Passed 0, Failed 8

&nbsp;&nbsp;&nbsp; If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

WR decoder status:

&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;Difference 
aida07 fault &nbsp;&nbsp; &nbsp; 0xc53d : &nbsp;&nbsp; &nbsp; 0xc5c9 : &nbsp;&nbsp; &nbsp; 140 &nbsp; 
aida08 fault &nbsp;&nbsp; &nbsp; 0xf1be : &nbsp;&nbsp; &nbsp; 0xf2b2 : &nbsp;&nbsp; &nbsp; 244 &nbsp; 
White Rabbit error counter test result: Passed 6, Failed 2

Understand the status reports as follows:- 
Status bit 3 : White Rabbit decoder detected an error in the received data 
Status bit 2 : Firmware registered WR error, no reload of Timestamp 
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR

FPGA timestamp check: 
&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp; Base &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Current &nbsp;&nbsp; &nbsp;&nbsp;&nbsp; &nbsp;Difference 
aida07 fault &nbsp;&nbsp; &nbsp; 0x2a : &nbsp;&nbsp; &nbsp; 0x41 : &nbsp;&nbsp; &nbsp; 23 &nbsp; 
FPGA Timestamp error counter test result: Passed 7, Failed 1 
If any of these counts are reported as in error 
The ASIC readout system has detected a timeslip. 
That is the timestamp read from the time FIFO is not younger than the last

At 4:15:

Stats ok - Attachment 7

Temp ok - Attachement 8

HV-LC -Attachment 9

Wide Checks: No change

At 7:15: (no beam since ~6am -&gt; background run)

Stats ok - Attachment 10

Temp ok - Attachement 11

HV-LC -Attachment 12

Wide Checks: No change

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Attachment 1: