AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
DESPEC
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Sat Mar 29 11:28:31 2025
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<p> <table width="98%" align="center" cellspacing="1" style="border:1px solid #486090;"> <tbody> <tr> <td cellpadding="3px" style="background-color:#486090; font-weidht:bold; color:white;">Quote:</td></tr> <tr> <td cellpadding="10px" style="background-color:#FFFFB0;"><p>0:00 Experiment continues to run smoothly. AIDA DAQ has been rather stable. Leakage current has gone up for the past two days in both DSSDs (combination of high-Z and high-intensity beam and external high temperature).</p> <p>Stats & Temperatures (VIRTEX,PSU, ASICs) all ok.</p> <p><strong>At 0:30 </strong></p> <p>Stats ok - Attachment 1</p> <p>Temp ok - Attachement 2</p> <p>HV-LC -Attachment 3</p> <p><strong>At 2:20</strong></p> <p>Stats ok - Attachment 4</p> <p>Temp ok - Attachement 5</p> <p>HV-LC -Attachment 6</p> <p>Wide Checks:</p> <p>Clock status test result: Passed 8, Failed 0 </p> <p> Understand status as follows<br /> Status bit 3 : firmware PLL that creates clocks from external clock not locked <br /> Status bit 2 : always logic '1'<br /> Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock<br /> Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock<br /> If all these bits are not set then the operation of the firmware is unreliable</p> <p>ADC Calibration (same as before):</p> <p> FEE64 module aida01 failed<br /> FEE64 module aida02 failed<br /> FEE64 module aida03 failed<br /> FEE64 module aida04 failed<br /> FEE64 module aida05 failed<br /> FEE64 module aida06 failed <br /> FEE64 module aida07 failed<br /> FEE64 module aida08 failed<br /> Calibration test result: Passed 0, Failed 8</p> <p> If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module</p> <p>WR decoder status:</p> <p> Base Current Difference<br /> aida07 fault 0xc53d : 0xc5c9 : 140 <br /> aida08 fault 0xf1be : 0xf2b2 : 244 <br /> White Rabbit error counter test result: Passed 6, Failed 2</p> <p>Understand the status reports as follows:-<br /> Status bit 3 : White Rabbit decoder detected an error in the received data<br /> Status bit 2 : Firmware registered WR error, no reload of Timestamp<br /> Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR</p> <p>FPGA timestamp check:<br /> Base Current Difference<br /> aida07 fault 0x2a : 0x41 : 23 <br /> FPGA Timestamp error counter test result: Passed 7, Failed 1<br /> If any of these counts are reported as in error<br /> The ASIC readout system has detected a timeslip.<br /> That is the timestamp read from the time FIFO is not younger than the last</p> <p><strong>At 4:15:</strong></p> <p>Stats ok - Attachment 7</p> <p>Temp ok - Attachement 8</p> <p>HV-LC -Attachment 9</p> <p>Wide Checks: No change</p> <p><strong>At 7:15: (no beam since ~6am -> background run)</strong></p> <p>Stats ok - Attachment 10</p> <p>Temp ok - Attachement 11</p> <p>HV-LC -Attachment 12</p> <p>Wide Checks: No change</p></td> </tr> </tbody> </table> </p><p> </p>
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