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AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40

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Entry time:	Fri Mar 15 16:29:57 2024
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The behaviour of the DSSSD leakage current at low voltages and during biases is unusual and varies depending on how the adapter boards are connected To summarise the behaviour I have observed Minimum bias configuration: 4 adapter boards, one n+n (LK1), three p+n (-ve bias), ground from n+n to one p+n Voltage (and leakage current) unstable at low voltages, seems to settle at around -60 V Drops can include 0 leakage current Full adapter configuration: 8 adapter boards, ground ring complete Same as minimum, but the drops seem to be much smaller (and not to 0 leakage current) -60V again seems to be the turnover to a stable leakage current In both cases the leakage current during ramping appears basically the same as when settled Full into FEEs 8 adapter boards, fully connected to 8 FEEs The leakage current is much higher during ramp,up to 17 uA near the end. No fluctuations Once ramping has finished the current quickly drops back down and settles at the nominal leakage current This has been observed in October/December too, it is not new (https://elog.ph.ed.ac.uk/AIDA/910) During power up of the FEEs the current sometimes drops briefly (when the ASICs get programmed, I believe) I think it is related to the ground (more or less current flowing through the HV supply instead of alternate paths?) It should be kept in mind when testing new detectors to not worry about the detector at low voltages Encoding: HTML ELCode plain Suppress Email notification Resubmit as new entry

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