Manual - see attachment 1


Internal configuration

Voltage full scale - 400V/10uA

JP1/1-4 fitted
JP4 fitted *see note below
DVM card JP1 AB
HV jumpers AB

Current readout resolution - 10nA

DVM card JP2 LM
JP5/1-5 GH


Polarity - channels 1-4 negative

Note with channel 1 voltage set to -180V the output voltage measured by DMM is -40V.
The output impedance of the Silena 7710 outputs may be comparable to the input impedance of the DMM (DMM typically c. 20-40M) so the measured voltage will be a *lower* 
limit.

With JP4 removed (per manual instructions for voltage full scale 400V/10uA) the front panel reads -20V with an output voltage measured by DMM of -40V.
Again, the measured voltage will be a lower limit.

By observation of the behaviour of the electronic noise of p+n junction and n+n Ohmic strips as a function of bias for MSL type W1 DSSSD 3353-4 (75um) the voltage 
applied to the DSSSD is > depletion.
MSL QA tests report depletion voltage 28V and test/operating voltage 28+10V = 38V.