New VHDL loaded in NNAIDA#11,#12,#13,#14: /MIDAS/Aida/FEE_Riken_Apr14_21.bin
The code introduces the feature of turning ON or OFF individual ASICs in a FEE64 card. This is achieved by turning off the clock signal to a individual ASIC, which then will not produce any data.
Feature controled through "ASIC readout bugger and control", by register onn base address 0x300 and offset 7 (until now 'ASIC readout enable').
Only basic tests of new VHDL were done, but the system seems to be working as before and the operation of turning off individual ASICs works as expected. Screenshot is sample of turning off ASIC3 in NNAIDA#12.
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