MACB configuration can be found at https://elog.ph.ed.ac.uk/AIDA/357

To investigate system-wide check clock status errors for nnaida5, 7, 8, 15 & 16
PJCS requests changing MACB #3 (5, 6, 13 & 14) mode from 3 to 0 (all other MACB
modes unchanged) followed by power-cycle of FEE64s

System-wide checks - see attachments 1-11
 No clock status errors observed for nnaida5
 N.B. nnaida23 fails clock status

Switch MACB #3 (7, 8, 15 & 16) from mode 0 to 3, and MACB #4 from 3 to 0
------------------------------------------------------------------------
System-wide checks - see attachments 12-21
 ReSync not complete for nnaida21, 22
 Clock status errors observed for 5, 7, 8, 15, 16 *and* 21, 22

Switch MACB #4 (21, 22, 29 & 30) from mode 0 to 3, and MACB #5 (7, 8, 15 & 16) from 3 to 0
------------------------------------------------------------------------------------------
System-wide checks - see attachments 22-28
 ReSync not complete for nnaida7, 8, 15 & 16
 Clock status errors observed for nnaida7, 8, 15 & 16 - status = 0

Switch MACB #5 (21, 22, 29 & 30) from mode 0 to 3 
-------------------------------------------------
System-wide checks - see attachments 29-33
 ReSync OK
 Clock status errors observed for nnaida5, 7, 8, 15 & 16 - status = various, bit 2 always set (as before)

Replace MACB #5 (was rev A, MACB serial #9) with MACB serial #13 (rev A, firmware 16.4.15) mode 3
-------------------------------------------------------------------------------------------------
System-wide checks - see attachments 34-36
 ReSync OK
 Clock status errors observed for nnaida5, 7, 8, 15 & 16 - status = various, bit 2 always set (as before)
 i.e. no change, MACB #5 NIM module not the problem

Replace MACB #1 (was rev B, MACB serial #21) with MACB serial #38 (rev B, firmware 16.4.15, internal CLK TERM
mod) mode 0
-------------------------------------------------------------------------------------------------------------------------
System-wide checks - see attachments 37-40
 ReSync OK
 *ALL* system-wide checks OK


Offline analysis of file Dec2016/R1_5 demonstrates ADC & disc data synchronised - see attachments 41 & 42