The Fast Trigger output of the FEE64 is formed from the OR of the four OR16 signals ( one from each of the ASICs.

The logic levels of the OR16 signals are active low in the FPGA and so if the are OR'd together then the output is inactive if any one of the ASICs is inactive.

This is a problem when the Fast Trigger is being used by other DAQ systems.

A new FPGA program 0x1b4FE01A ( version 26 ) is being compiled.

The Fast Trigger output will provide the logic AND of the four OR16 signals which should give the correct signal. This setting is selected by "Setup".

The other settings available using the Trigger register are shown below. Note that OR64 is the logic OR of the masked outputs of the ASIC individual Discriminator outputs.

when 0 => 

trigger_hit <= ASIC1_data_ready ;

when 1 =>

trigger_hit <= ASIC1_rdo_range  and ASIC1_data_ready ;

when 2 =>

trigger_hit <= ASIC2_rdo_range  and ASIC2_data_ready ;

when 3 =>

trigger_hit <= led_trigger(0) ;

when 4 =>

trigger_hit <= led_raw(0) ;

when 5 =>

trigger_hit <= chan_reset(0) ;

when 6 =>

trigger_hit <= force_capture_sync ;

when 7 =>

trigger_hit <= force_capture ;

when 8 =>

trigger_hit <= ASIC1_OR_16 ;

when 9 =>

trigger_hit <= ASIC2_OR_16 ;

when 10 =>

trigger_hit <= ASIC3_OR_16 ;

when 11 =>

trigger_hit <= ASIC4_OR_16 ;

when 12 =>

trigger_hit <= ASIC4_OR_16 and ASIC3_OR_16 and ASIC2_OR_16 and ASIC1_OR_16;

when 13 =>

trigger_hit <= led_trigger(1) ;

when 14 =>

trigger_hit <= OR64 ;

when 15 =>

trigger_hit <= ASIC4_OR_16 or ASIC3_OR_16 or ASIC2_OR_16 or ASIC1_OR_16;