AIDA GELINA BRIKEN nToF CRIB ISOLDE CIRCE nTOFCapture DESPEC DTAS EDI_PSA 179Ta CARME StellarModelling DCF K40
  DESPEC  ELOG logo
Message ID: 240     Entry time: Sun Apr 18 17:27:44 2021
Author: ML-OH 
Subject: system wide checks 

system wide checks at 6pm CET

##################################################

Difference noted from previous shift:

FPGS timestamp error 10 passed and 2 failed

##################################################


Clock status test result: Passed 12, Failed 0

Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable

ADC Calibration:

FEE64 module aida06 failed
FEE64 module aida07 failed
FEE64 module aida10 failed
Calibration test result: Passed 9, Failed 3

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

White Rabbit checks:

         Base         Current     Difference
aida01 fault      0x7686 :      0x768a :      4  
aida02 fault      0x941d :      0x9421 :      4  
aida03 fault      0x7cd7 :      0x7cdb :      4  
aida04 fault      0xb86d :      0xb871 :      4  
aida05 fault      0x1a59 :      0x1a61 :      8  
aida06 fault      0x4f45 :      0x4f4d :      8  
aida07 fault      0x3bfc :      0x3c11 :      21  
aida08 fault      0xc7ce :      0xc7d5 :      7  
aida09 fault      0xb33b :      0xb33c :      1  
White Rabbit error counter test result: Passed 3, Failed 9

Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR


FPGA timestamp errors checks:

             Base         Current         Difference
aida09 fault      0x1 :      0x2 :      1  
aida12 fault      0xa :      0xc :      2  
FPGA Timestamp error counter test result: Passed 10, Failed 2
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last

Memory information fro FEE64:

Returned 0 0 0 0 0 0 0 0 0 0 0 0  
Mem(KB) :    4    8    16    32    64    128    256    512    1k    2k    4k
aida01 :     27     16      4      2      2      2      1      3      3      3      6   : 36332
aida02 :     19      8      9      3      2      2      2      4      2      3      6   : 36092
aida03 :     23     10      8      6      4      4      3      3      2      3      6   : 36332
aida04 :     27      4      8      0      1      3      4      3      2      3      6   : 36044
aida05 :     21      6      5      4      4      2      2      2      2      4      6   : 37204
aida06 :     23     11      5      0      3      4      1      3      3      3      6   : 36548
aida07 :     14      9      5      2      3      3      2      2      4      3      6   : 37200
aida08 :     26      8      7      2      2      1      4      3      2      3      6   : 35928
aida09 :      2      3      4      1      1      3      3      4      2      3      6   : 36160
aida10 :     16      9      2      5      1      1      3      4      2      3      6   : 36104
aida11 :      7      5      0      0      3      3      1      4      2      3      6   : 35716
aida12 :      9      7      3      2      4      4      1      3      3      3      6   : 36556

 

 

 

Attachment 1: 18-04-2021_6pm_CAENHV.png  9 kB  Uploaded Sun Apr 18 18:38:42 2021  | Hide | Hide all
18-04-2021_6pm_CAENHV.png
Attachment 2: 18-04-2021_6pm_StatGoodEvent.png  79 kB  Uploaded Sun Apr 18 18:40:07 2021  | Hide | Hide all
18-04-2021_6pm_StatGoodEvent.png
Attachment 3: 18-04-2021_6pm_ADCdataItem.png  78 kB  Uploaded Sun Apr 18 18:40:26 2021  | Hide | Hide all
18-04-2021_6pm_ADCdataItem.png
Attachment 4: 18-04-2021_6pm_WR28-47#4.png  79 kB  Uploaded Sun Apr 18 18:40:49 2021  | Hide | Hide all
18-04-2021_6pm_WR28-47#4.png
Attachment 5: 18-04-2021_6pm_WR48-63#5.png  79 kB  Uploaded Sun Apr 18 18:41:01 2021  | Hide | Hide all
18-04-2021_6pm_WR48-63#5.png
Attachment 6: 18-04-2021_6pm_PauseInfo.png  70 kB  Uploaded Sun Apr 18 18:41:51 2021  | Hide | Hide all
18-04-2021_6pm_PauseInfo.png
Attachment 7: 18-04-2021_6pm_ResumeInfo.png  68 kB  Uploaded Sun Apr 18 18:42:02 2021  | Hide | Hide all
18-04-2021_6pm_ResumeInfo.png
Attachment 8: 18-04-2021_6pm_DiscInfo.png  76 kB  Uploaded Sun Apr 18 18:42:27 2021  | Hide | Hide all
18-04-2021_6pm_DiscInfo.png
Attachment 9: 18-04-2021_6pm_Correlation#8.png  74 kB  Uploaded Sun Apr 18 18:42:59 2021  | Hide | Hide all
18-04-2021_6pm_Correlation#8.png
Attachment 10: 18-04-2021_6pm_ucesb.png  150 kB  Uploaded Sun Apr 18 18:43:33 2021  | Hide | Hide all
18-04-2021_6pm_ucesb.png
Attachment 11: 18-04-2021_645pm_tempScan.png  97 kB  Uploaded Sun Apr 18 18:48:36 2021  | Hide | Hide all
18-04-2021_645pm_tempScan.png
Attachment 12: 18-04-2021_645pm_Spec1-8L.png  133 kB  Uploaded Sun Apr 18 19:23:29 2021  | Hide | Hide all
18-04-2021_645pm_Spec1-8L.png
Attachment 13: 18-04-2021_7pm_Spec1-8L_2.png  141 kB  Uploaded Sun Apr 18 19:23:40 2021  | Hide | Hide all
18-04-2021_7pm_Spec1-8L_2.png
Attachment 14: 18-04-2021_7pm_Spec1-8_layoutId4.png  168 kB  Uploaded Sun Apr 18 19:23:52 2021  | Hide | Hide all
18-04-2021_7pm_Spec1-8_layoutId4.png
Attachment 15: 18-04-2021_7pm_Spec1-8H.png  138 kB  Uploaded Sun Apr 18 19:24:08 2021  | Hide | Hide all
18-04-2021_7pm_Spec1-8H.png
Attachment 16: 18-04-2021_645pm_SpecRate.png  149 kB  Uploaded Sun Apr 18 19:25:14 2021  | Hide | Hide all
18-04-2021_645pm_SpecRate.png
Attachment 17: 18-04-2021_730pm_AIDA_LC.png  123 kB  Uploaded Sun Apr 18 21:50:45 2021  | Hide | Hide all
18-04-2021_730pm_AIDA_LC.png
ELOG V3.1.4-unknown