03:12 System Check
attachment 1 : Current
attachment 2 : Temperature
attachment 3 : Rates
Clock status test result: Passed 16, Failed 0
Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable
Calibration test result: Passed 16, Failed 0
If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module
Base Current Difference
aida05 fault 0x36ca : 0x36cb : 1
White Rabbit error counter test result: Passed 15, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
Base Current Difference
aida13 fault 0xa : 0xf : 5
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
Returned 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Mem(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 22 5 7 2 1 2 2 3 3 3 6 : 36464
aida02 : 9 8 3 3 1 4 1 2 4 3 6 : 36916
aida03 : 5 2 6 2 0 3 2 3 3 3 6 : 36420
aida04 : 6 5 2 3 4 4 2 3 3 3 6 : 36800
aida05 : 17 6 6 2 2 4 1 3 2 4 6 : 37524
aida06 : 7 12 3 4 3 3 1 3 3 3 6 : 36460
aida07 : 17 11 5 1 3 3 3 2 3 3 6 : 36428
aida08 : 3 5 0 1 4 2 2 4 2 3 6 : 35924
aida09 : 27 6 4 2 0 2 2 2 3 3 6 : 35868
aida10 : 16 11 8 0 2 2 1 3 2 4 6 : 37272
aida11 : 15 2 2 3 1 4 3 4 2 3 6 : 36364
aida12 : 1 6 4 3 1 3 2 4 2 3 6 : 35988
aida13 : 22 14 10 2 4 2 2 4 2 3 6 : 36264
aida14 : 26 10 4 3 2 1 1 3 3 3 6 : 36184
aida15 : 14 2 3 2 2 4 1 2 3 3 6 : 35896
aida16 : 7 5 4 0 2 4 2 3 2 3 6 : 35588
06:10 DSSD1 rate high!
Attached 4
Called OH and he woke up to fix it :)
It was a problem with one of the ASIC according to what he says:
One of the ASICs HEC was running crazy!. Forced the ASICs to check their settings which brings them to back into line see attachment 9. This done by around 06:35
07:03 System check
attachment 5 Spectrum rate
attachment 6 Voltages
attachment 7 Rates
attachment 8 Temperature
System wide clock are all ok except
White rabbit
Base Current Difference
aida05 fault 0x36ca : 0x36cb : 1
White Rabbit error counter test result: Passed 15, Failed 1
Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR
FPGA
Base Current Difference
aida13 fault 0xa : 0x14 : 10
FPGA Timestamp error counter test result: Passed 15, Failed 1
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last
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