Bias tests of AIDA on individual wafers and in parallel. Spreadsheet can be found in attachment 1, and graphic results can be seen in Attachment 2. Summary: Upstream detector cannot be biased in parallel nor individually. Downstream detector can be biased with positively and each wafer can individually be biased negatively. In parallel, it was not possible to bias the downstream detector negatively as indicated by the tests below.
Test downstream DSSSD with positive polarity bias
Configuration as follows:
CAEN N1419ET ch #3 connected to LHS FEE64 adaptor PCB ( looking upstream ) - LK1 *not* fitted LK1 fitted to 3x ( top )
FEE64 adaptor PCBs Lemo 00.250 jumper cables from/to GND terminals of 3x ( top )
FEE64 adaptor PCBs *and* LHS FEE64 adaptor PCB 1x ( bottom, middle )
FEE64 adaptor PCB connected to ribbon cables but not otherwise connected to anything, LK3 fitted Total 5x adaptor PCBs installed
No other LKs fitted
| Bias Voltage (V) |
Current (uA) |
| +10 |
2.150 |
| +20 |
3.300 |
| +30 |
4.035 |
| +40 |
4.550 |
| +50 |
4.955 |
| +60 |
5.255 |
| +70 |
5.490 |
| +80 |
5.650 |
| +90 |
5.730 |
| +100 |
5.780 |
| +110 |
5.825 |
| +120 |
5.860 |
Nominal V-I curve, stable leakage current. Attachment 3.
Following this success we attempted to repeat test using negative polarity bias
Configuration as follows:
CAEN N1419ET ch #1 connected to ( top, left )
FEE64 adaptor PCB ( looking upstream ) LHS
FEE64 adaptor PCB ( looking upstream ) - LK1 fitted Lemo 00.250 jumper cables from/to BIAS terminals of 3x ( top )
FEE64 adaptor PCBs Lemo 00.250 jumper cable from/to GND terminals of LHS and ( top, left )
FEE64 adaptor PCBs 1x ( bottom, middle )
FEE64 adaptor PCB connected to ribbon cables but not otherwise connected to anything,
LK3 fitted Total 5x adaptor PCBs installed No other LKs fitted With detector bias
-20V we continue to observe the leakage current cycling between 0 and ~2uA with a frequency ~1Hz ( as before )
Copy configuration used for upstream DSSSD test ( which was successful albeit there was detector breakdown at bias voltages > c. 90V )
CAEN N1419ET ch #1 connected to ( bottom, left )
FEE64 adaptor PCB ( looking upstream ) LHS
FEE64 adaptor PCB ( looking upstream ) - LK1 fitted Lemo 00.250 jumper cables from/to BIAS terminals of 3x ( bottom )
FEE64 adaptor PCBs Ground cable jumpered from/to GND terminals LHS, ( left, bottom ), RHS and all 3x top FEE64 adaptor PCBs ( bottom, middle )
FEE64 adaptor PCB LK3 fitted Total 8x adaptor PCBs installed
No other LKs fitted With detector bias -20V we observe leakage current of ~2-3uA.
Current unstable - variations 10-100nA over periods of several seconds Although the leakage current is unstable this is an improvement over previous tests with negative bias. The duplication of upstream and downstream configurations suggests that for some unknown reason it is necessary to connect all 8x FEE64 adaptor PCBs whereas our expectation was that only 4x were necessary.
Summary: Upstream DSSSD Si wafers 1 & 2 breakdown for bias > c. 90V Si wafer 3 OK to 120V Positive bias - not tested Negative bias OK - leakage current stable to c. 90V Downstream DSSSD Si wafers 1, 2 & 3 OK to 120V Positive bias OK Negative bias - leakage current unstable
To do:
1) Disconnect ribbon cables from p+n junction FEE64 adaptor PCBs of upstream DSSSD, apply c. 100V bias and check leakage current is zero i.e. eliminate shorts in PCBs
2) Check that all ribbon cables are properly seated in the adaptor PCBs
3) Check all adaptor PCB connector pins are OK: will need to remove ribbon cables
4) If/when you open check seating of all Kapton PCBs in the DSSSD connectors *and* carefully check that ribbon cable and Kapton PCB connectors are aligned and not out by 1 or 2 rows say.
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