10.00 DSSSD bias & leakasge current - Grafana - attachments 1-2

      FEE64 temperatures OK - attachment 3

      ADC data item stats - attachment 4
       9/16 FEE64s < 20k 

      per FEE64 Rate spectra - attachment 5

      Merger etc - attachments 6-7
       aida02, aida04 inactive

11.20 DAQ restarted
      aida02 and aida04 now producing data


11.30 analysis data file R22_313
      all deadtimes <1%
      no timewarps
      HEC data item rate 560Hz (all from one channel of aida08 asic #3)
      aida03 & aida04 MBS rates c. 24kHz


14.32 FEE64 temperatures OK
      ADC data item stats OK
       all FEE64s producing data

14.43 all histograms & stats zero'd

[NH checks here]

21.26 aida04 stopped forwarding to merger
 the "quick fix" (stop merger, rerun) worked

MBS is having huge issues on DESPEC side, AIDA not included
Decide to stop taking data to disk for now (no storage mode on)
Keeping running (incl. to AIDA FDR MBS) just to get an idea of stability

System Wide Checks
 clocks PASSED
 ADC IGNORED
 WR:
		 Base 		Current 	Difference
aida02 fault 	 0xe4d8 : 	 0x65c0 : 	 -32536  
aida03 fault 	 0x2371 : 	 0x2380 : 	 15  
aida04 fault 	 0xa210 : 	 0xaf58 : 	 3400  
aida06 fault 	 0x3624 : 	 0x3626 : 	 2  
White Rabbit error counter test result: Passed 12, Failed 4

FPGA: 
	
			 Base 		Current 		Difference
aida02 fault 	 0xaa3b : 	 0xc455 : 	 6682  
aida04 fault 	 0x5a4 : 	 0x6ba : 	 278  
aida06 fault 	 0x0 : 	 0x1 : 	 1  
FPGA Timestamp error counter test result: Passed 13, Failed 3
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last

Module aida04 LMK PLL channel 1 lock transition counter has incremented
Module aida04 LMK PLL channel 2 lock transition counter has incremented
PLL lock counter test result: Passed 15, Failed 1

Baselines reset

22.50 FEE64 temps ok
      merger ok
       all links active
      ADC data item stats ok