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AIDA
GELINA
BRIKEN
nToF
CRIB
ISOLDE
CIRCE
nTOFCapture
DESPEC
DTAS
EDI_PSA
179Ta
CARME
StellarModelling
DCF
K40
MONNET
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| DESPEC |
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Message ID: 749
Entry time: Mon Apr 20 11:05:00 2026
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| Author: |
TD |
| Subject: |
Saturday 18 April 2026 |
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Check of cooling water flow
- pressure (c. 7bar) and temperature (c. 20 deg C, above local dew point) at entrance to S4 OK - attachment 1
- USB-controlled ac mains relay - water flow/local humidity interlock OK (yellow LED)
- can feel flow in FEE64 coolant pipework
Disconnect ribbon cabling from snout to FEE64 adaptor PCB
Note FEE64 aida16 uses rev A adaptor PCB *without* grounding (expected to be noisy but OK for test purposes)
FEE64 power ON
Attachment 2 - FEE64 temperatures OK
Attachments 3-6 - System wide checks OK *except* aida02 WR timestamp/FPGA warnings (not a problem)
Attachment 7 - WR timestamps OK
Note PC with PEXARIA5 PCI card for AIDA WR timestamp data (to 'root' MACB input) was restarted but BuTIS input not available so WR data shows time from zero/power up *not* UNIX epoch time
Attachment 8 - ASIC settings 2025Jun14-15.00.09 restored
BNC PB-5 settings
Amplitude 1.0V or 2.0V
Attenuation x1
t_r 50ns
tau_d 1ms
Polarity + (p+n FEE64s) or - (n+n FEE64s)
Frequency 50Hz
n+n FEE64s
Attachment 9 - per FEE64 Rate spectra
Attachment 10 - ADC data item statistics
Attachments 11-13 - per n+n FEE64 1.8.L and 1.8.W spectra (20us FSR)
aida02 pulser peak width 16ch FWHM (11keV FWHM)
note common x and y scaling
with zero input load (capacitance and leakage current) expect pulser peak widths c. 10-15ch FWHM (c. 7-11keV FWHM)
p+n FEE64s
Attachment 14 - per FEE64 Rate spectra
aida16 asic#2 u/s?
Attachments 15-17 - per p+n FEE64 1.8.L and 1.8.W spectra (20us FSR)
aida09 pulser peak width 16ch FWHM (11keV FWHM)
note common x and y scaling
with zero input load (capacitance and leakage current) expect pulser peak widths c. 10-15ch FWHM (c. 7-11keV FWHM)
aida16 spectra noisy as expected
FEE64 power OFF
Switch config to 6x FEE64s (DSSSD#1 p+n FEE64s)
FEE64 power ON
Attachment 18 - FEE64 temperatures OK
Attachments 19-23 - system wide checks OK except ADC calibration due to ASIC synchronisation - need to re-run ADC calibration as usual
Attachment 24 - WR timestamps OK
Attachment 25 - ASIC settings saved 2026Apr18-15.26.25
Attachment 26 - ADC data item stats OK *except* aida16 asic#2 u/s?
Attachment 27 - per FEE64 Rate spectra
Attachment 28 - per p+n FEE64 1.8.L spectra
aida10 pulser peak width 15 ch FWHM (10.5keV FWHM)
note common x and y scale
Attachment 29 - ADC calibration OK
Attachments 30-32 - per p+n FEE64 1.8.W specra (20us FSR)
note AD9222 octal, 14 bit, 50MSPS ADC +/-1V input => 1LSB = 122uV
FEE64 power OFF
Mechanical check of all FEE64 and MCB HDMI connectors - all OK |
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