03:12系统检查

附件 1：当�

附件2：温度

附件3：费�

   
时钟状�测试结�：通过 16 项，失败 0 项

状��解如下
：状�� 3：固件 PLL（用��外部时钟生�时钟）未�定；
状æ€�ä½� 2：始终为逻辑“1”
；状�� 1：LMK3200(2) PLL 和时钟分�芯片未�定到外部时钟；
状�� 0：LMK3200(1) PLL 和时钟分�芯片未�定到外部时钟。
如�所有这些�都未设置，则固件�行���。

   
校准测试结�：通过 16 项，未通过 0 项

如�任何模�校准失败，请检查时钟状�并打开 FADC 校准和�制�览器页�，�新�行该模�的校准。

   
         基准电æµ�差值
aida05 æ•…éšœ 0x36ca : 0x36cb : 1  
白兔错误计数器测试结�：通过 15，失败 1

状�报告的�义如下：-
状�� 3：White Rabbit 解�器检测到�收到的数�有误；
状�� 2：固件记录了 WR 错误，时间戳未�新加载；
状�� 0：White Rabbit 解�器报告无法确定�自 WR 的时间戳信�。

   
             基准电æµ�差值
aida13 æ•…éšœ 0xa : 0xf : 5  
FPGA 时间戳错误计数器测试结�：通过 15，失败 1。
如�这些计数中有任何一项被报告为错误，则
表示 ASIC 读�系统检测到了时间滑移。
也就是说，� FIFO 读�的时间戳�比上一次读�的时间戳更新。

   
è¿”å›� 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0  
内存(KB) : 4 8 16 32 64 128 256 512 1k 2k 4k
aida01 : 22 5 7 2 1 2 2 3 3 3 6 : 36464
aida02 : 9 8 3 3 1 4 1 2 4 3 6 : 36916
aida03 : 5 2 6 2 0 3 2 3 3 3 6 : 36420
aida04 : 6 5 2 3 4 4 2 3 3 3 6 : 36800
aida05 : 17 6 6 2 2 4 1 3 2 4 6 : 37524
aida06 : 7 12 3 4 3 3 1 3 3 3 6 : 36460
aida07 : 17 11 5 1 3 3 3 2 3 3 6 : 36428
aida08 : 3 5 0 1 4 2 2 4 2 3 6 : 35924
aida09 : 27 6 4 2 0 2 2 2 3 3 6 : 35868
aida10 : 16 11 8 0 2 2 1 3 2 4 6 : 37272
aida11 : 15 2 2 3 1 4 3 4 2 3 6 : 36364
艾达12 : 1 6 4 3 1 3 2 4 2 3 6 : 35988
aida13 : 22 14 10 2 4 2 2 4 2 3 6 : 36264
aida14 : 26 10 4 3 2 1 1 3 3 3 6 : 36184
aida15 : 14 2 3 2 2 4 1 2 3 3 6 : 35896
aida16 : 7 5 4 0 2 4 2 3 2 3 6 : 35588

06:10 DSSD1 �高�

附件 4

我给�公打了电�，他起�就�修好了 :)

�他所说，问题出在澳大利亚�券�投资委员会（ASIC）的�个部门：

其中一�ASIC HEC芯片�行异常�强制ASIC芯片检查其设置，使其��正常（�附件9）。此�作大约在06:35完�。

07:03 系统检查

附件 5 频谱速�

附件 6 电�

附件 7 费�

附件 8 温度

系统时钟一切正常，除了

白兔

 åŸºå‡†ç”µæµ�差值
aida05 æ•…éšœ 0x36ca : 0x36cb : 1  
白兔错误计数器测试结�：通过 15，失败 1

状�报告的�义如下：-
状�� 3：White Rabbit 解�器检测到�收到的数�有误；
状�� 2：固件记录了 WR 错误，时间戳未�新加载；
状�� 0：White Rabbit 解�器报告无法确定�自 WR 的时间戳信�。

FPGA

 åŸºå‡†ç”µæµ�差值
aida13 æ•…éšœ 0xa : 0x14 : 10  
FPGA 时间戳错误计数器测试结�：通过 15，失败 1。
如�这些计数中有任何一项被报告为错误，则
表示 ASIC 读�系统检测到了时间滑移。
也就是说，� FIFO 读�的时间戳�比上一次读�的时间戳更新。

FEE64 module aida09 global clocks failed, 6
 Clock status test result: Passed 13, Failed 1

Understand status as follows
Status bit 3 : firmware PLL that creates clocks from external clock not locked
Status bit 2 : always logic '1'
Status bit 1 : LMK3200(2) PLL and clock distribution chip not locked to external clock
Status bit 0 : LMK3200(1) PLL and clock distribution chip not locked to external clock
If all these bits are not set then the operation of the firmware is unreliable

FEE64 module aida02 failed
FEE64 module aida06 failed
FEE64 module aida09 failed
FEE64 module aida10 failed
FEE64 module aida13 failed
Calibration test result: Passed 9, Failed 5

If any modules fail calibration , check the clock status and open the FADC Align and Control browser page to rerun calibration for that module

White Rabbit error counter test result: Passed 14, Failed 0

Understand the status reports as follows:-
Status bit 3 : White Rabbit decoder detected an error in the received data
Status bit 2 : Firmware registered WR error, no reload of Timestamp
Status bit 0 : White Rabbit decoder reports uncertain of Timestamp information from WR

FPGA Timestamp error counter test result: Passed 14, Failed 0
If any of these counts are reported as in error
The ASIC readout system has detected a timeslip.
That is the timestamp read from the time FIFO is not younger than the last

Some FEES were not acquiring data for some reason we could not understand. We lowered the thresholds to 200 keV, then rose them again to 700 keV. It seems they are now acquiring. We start data taking again.

- Bias and basic checks: the pulser FWHM appears to be ~170, which is the same we have obtained at the end of last week.

- Initialised the Merger and Tape server

- loading of settings: EXPERIMENTS/AIDA/2025Nov03-16.21.44

- slow comparator thresholds set to 700 keV for all X FEES

- y FEEs disabled in the discriminator

- Starting data taking with following details:

MIDAS data in: Bi207Centre_700

MBS data in /lustre/despec/aida_sourcetest_2025/raw started from lxg3138 on screen ('AIDAdaq')

We take data overnight in this configuration and continue the grounding checks tomorrow

- Initialised the Merger and Tape server

- loading of settings: EXPERIMENTS/AIDA/2025Oct29-16.11.06

- aida16 very noisy (attachments 3,4), slow comparator thresholds was risen to 500 keV, until reducing its deadtime to 0

- y FEEs disabled in the discriminator (example in attachment 5)

- Starting data taking with following details:

MIDAS data in: Bi207Centre

MBS data in /lustre/despec/aida_sourcetest_2025/raw started from lxg3138 on screen ('AIDAdaq')