While investigating a VHDL conundrum I have noticed that the Mux ADC serial readout clock has a 'FAST' slew rate on ASICs 1&2 and a normal slew rate on ASICs 3&4.

Is it possible that the higher slew rate is actually better filtered by the ASIC de-coupling etc than the slower one.

Unfortunately I can't  try this out yet as the "conundrum" means the VHDL version isn't good enough just yet.

Hopefully today.....

Patrick