Started AIDA at 11:50, writing to disk: file BG18OCT2/R3, stopped around 3 pm

pict1: HV supply
pict2: temperature
pict3: spectrum in stat, layout2
pict4: statistics

Started AIDA at 3:05pm, writing to disk: file BG18OCT2/R4, stopped 18.30

pict1: HV supply
pict2: temperature
pict3: spectrum in stat, layout2
pict4: statistics

pict5: sum spectra at 18:20 (3.4 hours)

system power off and unbiased

Started AIDA at 11:54am, writing to disk: file BG18OCT2/R5, stopped at 19:14

pict1: HV supply
pict2: temperature
pict3: spectrum in stat, layout2
pict4: statistics

pict5: sum spectra at 18:20 (3.4 hours)

system power off and unbiased

Started AIDA at 1:41 pm, writing to disk: file BG18OCT2/R6, stopped at  17:26
pict1: HV supply
pict2: temperature
pict3: spectrum in stat, layout2
pict4: statistics

stop the daq

pause merger

stop TapeServer

housekeeping checks

bias off

individually turn power relays off

switch off 2x NIN bins, 1x fan tray

do not turn off clock!!

turn off aida circuits at power box (careful!)

turn chiller off - press and hold arrow button

front panel switch on chiller - off

wall 3 phase power - off

withdraw aida clear from DTAS - slowly!

return power tool, temperature probe and water container to corral

*if cables*

network cables - blue, disconnect at switch, reel up at stairwell

disconnect clock

aida plastic high voltage and signal

cables from root macb trigger and reset to DTAS

mains cables from mains box

then move aida!

After starting run 1112, we noticed that the merge program was waiting for a first sync. It then turned out that all syncs had disappeared. This required an entire reboot of the AIDA DAQ. Consequently, AIDA run 1112 should not be used.

Here are some pictures after AIDA's relocation.

In principle, it can stay here, but probably after the tests we will push it further against the wall.  However, power and ethernet cabling cannot reach that far.

Attachment 1: Shows EURICA (original position) B-RIKEN moderator (near old AIDA spot) and AIDA (pushed downstream, rotated 90 degrees counterclockwise)

Attachment 2: Zoom in on AIDA from above.  Nominally the beam left downstream perspective.  Power supply is also seen on BRIKEN moderator table.

Attachment 3: Zoom in further of above, namely near FEE power supply rack

Attachment 4: More upstream view, still on beam left, showing tube with SSDs as well as water cooler in background

Attachment 5: Beam right view

Attachment 6: Beam right view from more upstream perspective, also showing the full tower of electronics.

AA informs me that the *centre* of the DTAS detector system is 26.7cm downstream
of the upstream edge of the upstream DTAS NaI(Tl) detectors.

The 6x DSSSDs are currently positioned per the 8x DSSSD setup of June 2018, i.e.
the 6x DSSSDs are in positions 3-8 (as indicated on the AIDA snout). 

Detectors #4 & #5 are centred ~9cm from upstream edge of AIDA snout.

This means that the upstream edge of the AIDA snout should be 26.7-9=17.7cm 
from the upstream edge of the upstream DTAS NaI(Tl) detectors.

Attachments  1-23 AIDA FEE64s nnaida1-nnaida23 ASIC #1 waveforms

Attachments 24-27 AIDA FEE64 nnaida24 ASIC #1 - #4 waveforms

Common y-scale 7000-9000, xscale ~1000 samples @ 20ns/sample

All *L and *W histograms saved to /MIDAS/SpecData at c. 17.00 Saturday 4 June 2016

Note

1) BNC PB-4 Pulser amplitude 90,000, x5 attenuator, frequency c. 5Hz + ~40kBq 60Co source
placed on AIDA snout

2) EURICA closed

To make room for the installation of an MR-TOF device at F11, AIDA and DTAS have been removed 
from their in-beam position at F11.

The AIDA network and DTAS/BRIKEN optic fibre cables have been coiled and tied to the E17 stairwell
barrier.

Honeywell HSS DPS sensor information https://elog.ph.ed.ac.uk/AIDA/932

Cynergy3 FSVPLC - attachment 1


Honeywell sensor - red LED continuously lit - OK

Connecting FSVPLC to the interlock box causes green power LED of 24V adaptor to blink ~Hz frequency indicating a fault condition

Developing real-time AIDA data synchronisation test using MIDASsort

To illustrate AIDA readout, ADC and discriminator data from a pulser event is plotted as a function
of the 100MHz AIDA internal timestamp (1us/channel)

Attachment 1 -    nnaida8  number of ADC and discriminator data items
Attachment 2 - nnaida1-24  number of ADC and discriminator data items
Attachment 3 - 4*(FEE64 module # - 1) + ASIC # (ADC channels 0-95, disc channels 100-195) versus timestamp
(1us/channel)

The spectra clearly illustrate

- 500kHz ADC readout cycle
- discriminator readout precedes ADC readout by ~18us (this figure will be shaping time dependent)
- after-pulse due to pulser injection via simple charge terminator (no pole zero correction) 
  ~84us after start of ADC readout (this figure will be pulser decay time and shaping time dependent)

Note events were identified (delimited) by time periods > 2us between successive ADC data items  

This is a short list of things todo or check before the test beam time on 11.12.23 
Updated after 15:00 CET meeting

1. Replace water interlock
- Also allows testing of AIDA for 24h+ 

2. Decide on snout configuration: 1 or 2 BB18s (plus BB7 plus bPlastic)
  It is U so if we put 2 we could damage 2 instead of just 1 (of course we try to be careful)
  To decide which bPlas is installed (only 1 will be bothered): Upstream is preferred by HA
  Install Peter's light blocking frame between bPlastic and AIDA

3. Replace aida04 with a working FEE64
  Important as aida04 is in deadtime and not very useful

4. Investigate/replace aida06 
  Less urgent because 2 strips and runs with 0 dead time

5. If 2 BB18s, add another 8 working FEE64s to the system
  Note: Cannot do 2BB18s and 1BB7 (cannot power/cool 17 FEEs)

6. Test AIDA firmware fix for individual ASIC controls (especially if BB7<->AIDA will be tested)
  BB7<->AIDA will not be tested probably, as PCB will not arrive.
  Still good to check if possible

7. Decide on FEE to take pulser (assuming no distribution/inverter available)
  Test implant response with pulser and SC41 trigger?

In no particular order of priority:

1) Vary ASIC V_DD=3.3V within +/-10% operating range

2) Use 'clean' floating high voltage detector bias
    - check polarity
    - is there a difference between detector local
      ground on p+n junction or n+n ohmic sides of DSSSD? 
    - common or isolated detector local ground for multiple DSSSDs?
    - RFQ submitted for 1x CAEN N1419
    - additional filtering for Emco Q05-5?
    - other?

3) Backtrack changes to date
     - Kapton PCB mods
     - PSU set points
     - Standard FEE64 PSUs -> linearly regulated PSUs

4) Evaluate effect of ASIC parameters 'Ibias preamp SF' and 'Ibias preamp' on noise

5) Evaluate effect of ASIC parameter 'preAmp reference' on stability of positive and 
   negative input configurations

Comments and corrections welcome!